Semiconductor device

ABSTRACT

High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

An embodiment of the invention disclosed in this specification and the like relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that a semiconductor device in this specification and the like refers to any device that can function by utilizing semiconductor characteristics, and for example, electro-optical devices, image display devices, semiconductor circuits, and electronic devices are all semiconductor devices.

2. Description of the Related Art

A technique by which transistors are formed using semiconductor thin films formed over a substrate having an insulating surface has been attracting attention. Such a transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor. As another material, an oxide semiconductor has been attracting attention.

For example, a technique by which a transistor is formed using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

Non-Patent Document 1 discloses a transistor including a stack of oxide semiconductors. However, in the structure disclosed in Non-Patent Document 1, the oxide semiconductor functioning as a channel is in contact with a silicon oxide film; thus, silicon, a constituent element of the silicon oxide film, might be mixed into the channel as an impurity. The impurity mixed into the channel causes degradation of the electrical characteristics of the transistor.

REFERENCE Patent Document

[Patent Document 1] Japanese Published Patent Application No. 2007-123861

[Patent Document 2] Japanese Published Patent Application No. 2007-096055

Non-Patent Document

[Non-Patent Document 1] Arokia Nathan et al., “Amorphous Oxide TFTs: Progress and Issues”, SID 2012 Digest, pp. 1-4

SUMMARY OF THE INVENTION

Electrical characteristics of a transistor including an oxide semiconductor vary depending on an interface state between an oxide semiconductor layer and an insulating layer in contact with the oxide semiconductor layer.

For example, interface scattering of carriers at the interface between the oxide semiconductor layer and the insulating layer in contact with the oxide semiconductor layer causes degradation of the field-effect mobility of the transistor. Moreover, if a trap level (also referred to as an interface state) exists at that interface, the trap level causes a change in the electrical characteristics (e.g., the threshold voltage, the subthreshold swing (S value), or the field-effect mobility) of the transistor.

Thus, an object of one embodiment of the present invention is to provide high field-effect mobility for a semiconductor device including an oxide semiconductor.

Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor by preventing a change in its electrical characteristics.

One embodiment of the present invention is a transistor which has a structure in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween. In the transistor, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers which have lower carrier density than the oxide semiconductor layer and function as buffer layers for stabilizing an interface between the channel and an insulating layer. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed. Further, the oxide semiconductor layer functioning as the channel contains an impurity imparting n-type conductivity (also referred to as an n-type impurity) and shows variation in concentration of the n-type impurity in the thickness direction. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side (also simply referred to as the channel side) contains the n-type impurity at a higher concentration than a region on the back channel side. Accordingly, off-state current can be controlled while on-state characteristics (e.g., on-state current and field-effect mobility) of the transistor are improved. Specifically, the following structure can be employed for example.

One embodiment of the present invention is a semiconductor device including a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor stack overlapping with the gate electrode layer with the gate insulating layer provided therebetween and having a stacked-layer structure of a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stack. In the semiconductor device, the second oxide semiconductor layer contains an n-type impurity, and a region of the second oxide semiconductor layer in contact with the first oxide semiconductor layer contains the n-type impurity at a higher concentration than a region of the second oxide semiconductor layer in contact with the third oxide semiconductor layer.

Another embodiment of the present invention is a semiconductor device including a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor stack overlapping with the gate electrode layer with the gate insulating layer provided therebetween and having a stacked-layer structure of a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stack. In the semiconductor device, the second oxide semiconductor layer contains an n-type impurity, a region of the second oxide semiconductor layer in contact with the first oxide semiconductor layer contains the n-type impurity at a higher concentration than a region of the second oxide semiconductor layer in contact with the third oxide semiconductor layer, and the first to third oxide semiconductor layers contain at least one common metal element.

In the above semiconductor device, it is preferable that the thickness of the first oxide semiconductor layer be smaller than the thickness of the second oxide semiconductor layer, and the thickness of the third oxide semiconductor layer be larger than or equal to the thickness of the second oxide semiconductor layer.

In the above semiconductor device, the first oxide semiconductor layer and the third oxide semiconductor layer are preferably i-type oxide semiconductor layers.

In the semiconductor device, it is preferable that the third oxide semiconductor layer be provided to cover the first oxide semiconductor layer and the second oxide semiconductor layer.

Effects of a structure of one embodiment of the present invention are described below with reference to FIG. 1. FIG. 1 is an example of an energy band structure of an oxide semiconductor stack, which shows the relation between the bottoms of the conduction band (Ec) and the Fermi level (Ef).

A transistor of one embodiment of the present invention includes an oxide semiconductor stack including a first oxide semiconductor layer S1 in contact with a gate insulating layer (a stacked-layer structure of a silicon nitride (SiN_(x)) layer and a silicon oxide (SiO_(x)) layer in FIG. 1), a second oxide semiconductor layer S2 on and in contact with the first oxide semiconductor layer S1, and a third oxide semiconductor layer S3 on and in contact with the second oxide semiconductor layer S2.

In the oxide semiconductor stack, the second oxide semiconductor layer S2 which is sandwiched between the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3 has higher conductivity σ than the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3 and functions as a channel. The second oxide semiconductor layer S2 is an oxide semiconductor layer containing an n-type impurity and shows variation in concentration of the n-type impurity in the thickness direction. In FIG. 1, the second oxide semiconductor layer S2 includes a first region S21 which is in contact with the first oxide semiconductor layer S1 and contains the n-type impurity at a high concentration, and a second region S22 which is in contact with the third oxide semiconductor layer S3 and contains the n-type impurity at a lower concentration than the first region S21. For example, in the case where the first region S21 is a region having n⁺-type conductivity, the second region S22 is a region having n⁻-type conductivity. Alternatively, the first region S21 may be a region having n⁻-type conductivity and the second region S22 may be a region having i-type conductivity.

The second oxide semiconductor layer S2 containing the n-type impurity has higher carrier concentration than the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3. In addition, the Fermi level (Ef) is closer to bottoms (Ec) of the conduction band in the second oxide semiconductor layer S2 than to those of the conduction band in the first and third oxide semiconductor layers S1 and S3. Note that in FIG. 1, the second oxide semiconductor layer S2 includes the first region S21 and the second region S22, and the first region S21 contains the n-type impurity at a higher concentration than the second region S22. Therefore, the Fermi level (Ef) is closer to the bottom (Ec) of the conduction band in the first region S21 than to that of the conduction band in the second region S22.

In the second oxide semiconductor layer S2, the high concentration of the n-type impurity in the first region S21 on the gate insulating layer side leads to an improvement in the conductivity of the channel, so that high on-state current characteristics can be provided for the transistor. Further, the second region S22 having a lower concentration of the contained n-type impurity than the first region S21 is provided on the back channel side of the first region S21, whereby the off-state current of the transistor can be controlled, so that favorable transistor characteristics can be obtained.

Materials, compositions, crystal structures, and the like of the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3 are selected as appropriate so that the bottoms of the conduction band form a depression in the energy band diagram in which the second oxide semiconductor layer S2 is provided between the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3. For example, the first oxide semiconductor layer S1 and/or the third oxide semiconductor layer S3 are/is formed using a metal oxide which has smaller conductivity than the metal oxide contained in the second oxide semiconductor layer S2. Alternatively, energy differences between the bottoms of the conduction band may be formed by using oxide semiconductor layers which have a lower n-type impurity concentration than the second oxide semiconductor layer S2 (specifically, the second region S22) and preferably by using i-type (intrinsic) or substantially i-type oxide semiconductor layers, as the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3.

As illustrated in FIG. 1, in the structure where the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3 having a lower concentration of the n-type impurity than the second oxide semiconductor layer S2 containing the n-type impurity are provided with the second oxide semiconductor layer S2 sandwiched therebetween, the energy levels of the bottoms of the conduction band in the second oxide semiconductor layer S2 is lower than those in the first and third oxide semiconductor layers S1 and S3, so that an energy difference is generated between the bottoms of the conduction band. Accordingly, a structure in which carriers flow through a region which is separated from an insulating layer (the silicon oxide layer SiO_(x) in FIG. 1) in contact with the oxide semiconductor stack (what is called a buried channel) can be obtained. The second oxide semiconductor layer S2 serves as the buried channel, which allows a reduction in interface scattering of carriers. Consequently, high field-effect mobility can be achieved.

In addition, the interface between the channel and the insulating layer in contact with the top layer or the bottom layer of the oxide semiconductor stack can be stabilized, so that the influence of a trap level which might be formed at the channel-side interface or the back-channel-side interface can be reduced. A reduction in the influence of a trap level at the channel-side interface prevents degradation, in particular, photodegradation such as negative-bias temperature stress photodegradation, of the transistor; thus, the transistor can have high reliability. A reduction in the influence of a trap level at the back-channel-side interface enables control of the threshold voltage of the transistor.

The second oxide semiconductor layer S2 containing the n-type impurity has higher conductivity σ than the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3. Therefore, high field-effect mobility can be achieved in a transistor in which the second oxide semiconductor layer S2 serves as a channel.

Note that in the oxide semiconductor stack included in the transistor of one embodiment of the present invention, energy differences between the bottoms of the conduction band are formed by the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3 between which the second oxide semiconductor layer S2 containing the n-type impurity and functioning as the channel is sandwiched. Therefore, the energy band structure is not limited to that in FIG. 1 as long as the bottoms of the conduction band in the second oxide semiconductor layer S2 is lower than those of the first oxide semiconductor layer S1 and the third oxide semiconductor layer S3, i.e., as long as the bottoms of the conduction band form a depression in the energy band diagram.

An energy difference (built-in potential) between the bottoms of the conduction band in the first oxide semiconductor layer S1 and the second oxide semiconductor layer S2 or between the bottoms of the conduction band in the third oxide semiconductor layer S3 and the second oxide semiconductor layer S2 is preferably greater than or equal to 0.05 eV, further preferably greater than or equal to 0.1 eV.

The n-type impurity contained in the second oxide semiconductor layer S2 may be boron, nitrogen, phosphorus, or the like. An example of a method for introducing the impurity to obtain the n-type second oxide semiconductor layer S2 is to deposit the second oxide semiconductor layer S2 by a sputtering method in a mixed atmosphere containing nitrogen or dinitrogen monoxide. Alternatively, the second oxide semiconductor layer S2 may be deposited with use of a sputtering target containing a very small amount of boron or phosphorus.

In order that the concentration of the n-type impurity contained in the second oxide semiconductor layer S2 shows variation (has gradient), the following method can be employed, for example: the first region S21 is formed using a first sputtering target containing boron or phosphorus and then the second region S22 is formed using a second sputtering target having a lower concentration of boron or phosphorus than the first sputtering target, whereby the second oxide semiconductor layer S2 showing variation in concentration of the n-type impurity in the thickness direction can be formed. Note that in the case where a plurality of sputtering targets having different concentrations of boron or phosphorus is used for forming the second oxide semiconductor layer S2, metal oxides contained the sputtering targets preferably contain the same the constituent elements at the same compositions. Alternatively, the second oxide semiconductor layer S2 showing variation in concentration of the n-type impurity in the thickness direction may be formed in such a manner that the first region S21 is formed using a sputtering target containing boron or phosphorus while a nitrogen gas or a gas containing nitrogen, such as dinitrogen monoxide, is supplied to a deposition chamber, and then the second region S22 is formed using the same target while the supply of the nitrogen gas or the gas containing nitrogen is stopped.

As an oxide semiconductor which is applicable to the first oxide semiconductor layer S1, a material represented by In_(a)M1_(b)Zn_(c)O, (a is a real number greater than or equal to 0 and less than or equal to 2, b is a real number greater than 0 and less than or equal to 5, c is a real number greater than or equal to 0 and less than or equal to 5, and x is a given real number) can be used. A metal element such as Ga, Mg, Hf, Al, Sn, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu is contained as M1 to function as a stabilizer for stabilizing the electrical characteristics of the transistor.

As an oxide semiconductor which is applicable to the second oxide semiconductor layer S2, a material represented by In_(d)M2_(e)Zn_(f)O_(x) (d is a real number greater than 0 and less than or equal to 5, e is a real number greater than or equal to 0 and less than or equal to 3, f is a real number greater than 0 and less than or equal to 5, and x is a given real number) can be used. A metal element such as Ga, Mg, Hf, Al, Sn, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu is contained as M2 to function as a stabilizer for stabilizing the electrical characteristics of the transistor.

As an oxide semiconductor which is applicable to the third oxide semiconductor layer S3, a material represented by In_(g)M3_(h)Zn_(i)O_(x) (g is a real number greater than or equal to 0 and less than or equal to 2, h is a real number greater than 0 and less than or equal to 5, i is a real number greater than or equal to 0 and less than or equal to 5, and x is a given real number) can be used. A metal element such as Ga, Mg, Hf, Al, Sn, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu is contained as M3 to function as a stabilizer for stabilizing the electrical characteristics of the transistor.

Note that at least one of the constituent elements of the first oxide semiconductor layer 51 is a metal element which is a constituent element of the second oxide semiconductor layer S2. Further, at least one of the constituent elements of the third oxide semiconductor layer S3 is a metal element which is a constituent element of the second oxide semiconductor layer S2.

According to one embodiment of the present invention, high field-effect mobility can be achieved in a transistor including an oxide semiconductor.

Further, according to one embodiment of the present invention, a change in the electrical characteristics of a transistor including an oxide semiconductor can be prevented, so that a highly reliable semiconductor device can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a band diagram illustrating one embodiment of an oxide semiconductor stack.

FIGS. 2A to 2C are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 3A to 3E illustrate an example of a method for manufacturing a semiconductor device.

FIGS. 4A to 4C each illustrate one embodiment of a semiconductor device.

FIGS. 5A and 5B each illustrate one embodiment of a semiconductor device.

FIGS. 6A and 6B illustrate one embodiment of a semiconductor device.

FIGS. 7A and 7B illustrate one embodiment of a semiconductor device.

FIGS. 8A to 8C each illustrate an electronic appliance.

FIGS. 9A to 9C illustrate an electronic appliance.

FIGS. 10A to 10E illustrate an example of a method for manufacturing a semiconductor device.

FIG. 11 illustrates one embodiment of a semiconductor device.

FIG. 12 illustrates a deposition apparatus which can be used for manufacture of a semiconductor device.

FIG. 13A is a schematic view of a flat-plate-like sputtered particle. FIG. 13B illustrates a model of deposition. FIG. 13C is a model diagram illustrating a state of a flat-plate-like sputtered particle.

FIG. 14A illustrates a model of deposition. FIG. 14B is a model diagram illustrating a state where oxygen is released from a flat-plate-like sputtered particle.

FIGS. 15A and 15B illustrate a model of deposition. FIG. 15C is a model diagram illustrating a state of flat-plate-like sputtered particles.

FIGS. 16A to 16C are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 17A to 17D illustrate an example of a method for manufacturing a semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the description below and it is easily understood by those skilled in the art that the mode and details can be changed in various ways. Therefore, the invention should not be construed as being limited to the description in the following embodiments.

Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. Further, the same hatching pattern is applied to portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.

Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, embodiments of the present invention are not limited to such scales.

Note that the ordinal numbers such as “first” and “second” in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the present invention.

In this specification, a term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, a term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.

In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

Embodiment 1

In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device are described with reference to FIGS. 2A to 2C and FIGS. 3A to 3E. In this embodiment, a bottom-gate transistor including an oxide semiconductor layer is described as one example of a semiconductor device.

FIGS. 2A to 2C illustrate a structural example of a transistor 310. FIG. 2A is a plan view of the transistor 310, FIG. 2B is a cross-sectional view taken along X1-Y1 in FIG. 2A, and FIG. 2C is a cross-sectional view taken along V1-W1 in FIG. 2A.

The transistor 310 illustrated in FIGS. 2A to 2C includes a gate electrode layer 402 which is provided over a substrate 400 having an insulating surface, a gate insulating layer 404 over the gate electrode layer 402, an oxide semiconductor stack 408 which is on and in contact with the gate insulating layer 404 and overlaps with the gate electrode layer 402, and a source electrode layer 410 a and a drain electrode layer 410 b which are electrically connected to the oxide semiconductor stack 408. Further, an insulating layer 412 which covers the source electrode layer 410 a and the drain electrode layer 410 b and is in contact with the oxide semiconductor stack 408 may be included in the transistor 310 as a component. The channel length of the transistor 310 can be greater than or equal to 1 μm, for example.

In this embodiment, the gate insulating layer 404 has a stacked-layer structure of a gate insulating layer 404 a which is in contact with the gate electrode layer 402 and a gate insulating layer 404 b which is provided over the gate insulating layer 404 a and in contact with the oxide semiconductor stack 408. The insulating layer 412 has a stacked-layer structure of an insulating layer 412 a which is in contact with the source electrode layer 410 a and the drain electrode layer 410 b and an insulating layer 412 b which is provided over the insulating layer 412 a.

The oxide semiconductor stack 408 includes a first oxide semiconductor layer 408 a in contact with the gate insulating layer 404, a second oxide semiconductor layer 408 b on and in contact with the first oxide semiconductor layer 408 a, and a third oxide semiconductor layer 408 c on and in contact with the second oxide semiconductor layer 408 b and in contact with the source electrode layer 410 a and the drain electrode layer 410 b. The third oxide semiconductor layer 408 c is provided so as to cover a side surface of the first oxide semiconductor layer 408 a and a side surface of the second oxide semiconductor layer 408 b. The periphery of the third oxide semiconductor layer 408 c is in contact with the gate insulating layer 404.

Note that as the second oxide semiconductor layer 408 b, an oxide semiconductor layer containing an impurity imparting n-type conductivity (n-type impurity) is used. The second oxide semiconductor layer 408 b shows variation in concentration of the n-type impurity in the thickness direction. In the second oxide semiconductor layer 408 b, a region which is in contact with the first oxide semiconductor layer 408 a contains the n-type impurity at a higher concentration than a region which is in contact with the third oxide semiconductor layer 408 c. In this embodiment, the second oxide semiconductor layer 408 b includes a first region 408 b which is in contact with the first oxide semiconductor layer 408 a and contains the n-type impurity at a high concentration (has n⁺-type conductivity, for example), and a second region 408 b 2 which is in contact with the third oxide semiconductor layer 408 c and contains the n-type impurity at a lower concentration than the first region 408 b 1 (has n⁻-type conductivity, for example). Note that an embodiment of the present invention is not limited thereto. The second oxide semiconductor layer 408 b may have a concentration gradient in which the concentration of the n-type impurity successively decreases from the region in contact with the first oxide semiconductor layer 408 a toward the region in contact with the third oxide semiconductor layer 408 c.

Materials, compositions, crystal structures, and the like of the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c are selected as appropriate so that the bottoms of the conduction band form a depression in the energy band diagram in which the second oxide semiconductor layer 408 b is provided between the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c. For example, the first oxide semiconductor layer 408 a and/or the third oxide semiconductor layer 408 c are/is formed using a metal oxide which has smaller conductivity than the metal oxide contained in the second oxide semiconductor layer 408 b. When the oxide semiconductor layers have the same constituent elements, the first oxide semiconductor layer 408 a and/or the third oxide semiconductor layer 408 c may be formed to have a composition having a higher band gap. Alternatively, energy differences between the bottoms of the conduction band may be formed by using oxide semiconductor layers which have a lower n-type impurity concentration than the second oxide semiconductor layer 408 b (specifically, the second region 408 b 2) and preferably by using i-type (intrinsic) or substantially i-type oxide semiconductor layers, as the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c.

Note that the second oxide semiconductor layer 408 b containing the n-type impurity has higher conductivity σ than the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c. When the conductivity σ of the second oxide semiconductor layer 408 b is increased, a distance between the second oxide semiconductor layer 408 b and the drain electrode layer 410 b (the thickness of the third oxide semiconductor layer 408 c) becomes dominant, so that apparently, the channel length is reduced in the forward direction. Accordingly, the on-state current of the transistor can be improved. Further, in the reverse direction, the third oxide semiconductor layer 408 c is depleted, so that low off-state current can be expected.

In the oxide semiconductor stack 408, the second oxide semiconductor layer 408 b functioning as a channel contains the n-type impurity, whereby the carrier density of the channel can be increased and the Fermi level (Ef) in the energy band diagram is close to the conduction band side. As a result, the field-effect mobility of the transistor can be improved.

An oxide semiconductor layer containing the n-type impurity is used as the second oxide semiconductor layer 408 b, and the oxide semiconductor stack is formed so that an energy difference between the bottoms of the conduction band is formed between the second oxide semiconductor layer 408 b and the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c. For example, the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c between which the second oxide semiconductor layer 408 b is sandwiched have a lower n-type impurity concentration than the second oxide semiconductor layer 408 b, preferably are i-type oxide semiconductor layers. When there is an energy difference between the bottom of the conduction band in the second oxide semiconductor layer 408 b functioning as the channel and each of the bottoms of the conduction band in the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c, a structure in which carriers flow through a region which is apart from the insulating layer (the gate insulating layer 404 and/or the insulating layer 412) in contact with the oxide semiconductor stack 408 (i.e., a buried channel) can be obtained. When the second oxide semiconductor layer 408 b serves as a buried channel, interface scattering of carriers is reduced. As a result, high field-effect mobility can be achieved.

Further, when the first region 408 b 1 positioned on the gate insulating layer side contains the n-type impurity at a higher concentration than the second region 408 b 2 positioned on the back channel side in the second oxide semiconductor layer 408 b, the off-state current of the transistor can be controlled while the on-state characteristics (e.g., on-state current and field-effect mobility) of the transistor are improved.

Energy differences (built-in potential) between the bottoms of the conduction band in the first oxide semiconductor layer 408 a and the first region 408 b 1 of the second oxide semiconductor layer 408 b and between the bottoms of the conduction band in the third oxide semiconductor layer 408 c and the second region 408 b 2 of the second oxide semiconductor layer 408 b are preferably greater than or equal to 0.05 eV, further preferably greater than or equal to 0.1 eV.

The first oxide semiconductor layer 408 a prevents capture of carriers at the interface between the channel and the gate insulating layer, so that photodegradation (e.g., negative-bias temperature stress photodegradation) of the transistor can be reduced, which enables the transistor to have high reliability.

In general, an oxide semiconductor layer is mostly formed by a sputtering method. On the other hand, when the oxide semiconductor layer is formed by sputtering, in some cases, an ionized rare gas element (e.g., argon) or an element ejected from a surface of a sputtering target flicks off a constituent element of a film, such as a gate insulating layer, on which the oxide semiconductor layer is to be formed. The element flicked off from the film on which the oxide semiconductor layer is to be formed might enter the oxide semiconductor layer and function as an impurity element therein. In particular, a portion of the oxide semiconductor layer, which is in the vicinity of the surface on which the oxide semiconductor layer is formed, might have high concentration of the impurity element. Further, when the impurity element remains in the vicinity of the surface where the oxide semiconductor layer is to be formed, the resistance of the oxide semiconductor layer is increased, which causes the electrical characteristics of the transistor to be lowered.

However, in the transistor 310, since the first oxide semiconductor layer 408 a is provided between the gate insulating layer 404 and the second oxide semiconductor layer 408 b in which the channel is formed, a constituent element of the gate insulating layer 404 can be prevented from diffusing to the channel. That is, the first oxide semiconductor layer 408 a may contain the constituent element (e.g., silicon) of the gate insulating layer 404 as an impurity. By including the first oxide semiconductor layer 408 a, the transistor 310 can have more stabilized electrical characteristics; thus, a highly reliable semiconductor device can be provided.

The third oxide semiconductor layer 408 c provided on the back-channel side of the second oxide semiconductor layer 408 b reduces the influence of a trap level at the back-channel-side interface of the transistor 310. For example, the third oxide semiconductor layer 408 c can prevent a constituent element of the source and drain electrode layers 410 a and 410 b from diffusing into the second oxide semiconductor layer 408 b. That is, the third oxide semiconductor layer 408 c might contain the constituent element (e.g., copper) of the source and drain electrode layers 410 a and 410 b, as an impurity. Thus, since formation of a trap level in the channel of the transistor can be prevented when the third oxide semiconductor layer 408 c is provided, an increase in 8 value due to the trap level and/or control of the threshold voltage can be performed. When the threshold voltage is controlled with the third oxide semiconductor layer 408 c, the transistor can be made normally off.

The thickness of the first oxide semiconductor layer 408 a, which reduces the influence of a trap level at the channel-side interface and stabilizes the electrical characteristics of the transistor, can be, for example, greater than or equal to 3 nm and less than or equal to 20 nm or greater than or equal to 5 nm and less than or equal to 10 nm By forming the first oxide semiconductor layer 408 a to the above thickness, even when the first oxide semiconductor layer 408 a contains the constituent element of the gate insulating layer 404 as an impurity, the impurity can be prevented from reaching the second oxide semiconductor layer 408 b functioning as the channel. The thickness of the second oxide semiconductor layer 408 b functioning as a channel (the total thickness of the first region 408 b 1 and the second region 408 b 2) is preferably greater than or equal to 10 nm and less than or equal to 40 nm, further preferably greater than or equal to 15 nm and less than or equal to 30 nm. The thickness of the third oxide semiconductor layer 408 c, which reduces the influence of a trap level at the back-channel-side interface and enables control of the threshold voltage, can be greater than or equal to 10 nm and less than or equal to 40 nm or greater than or equal to 15 nm and less than or equal to 30 nm, for example.

Note that as described above, the thickness of the third oxide semiconductor layer 408 c can be the substantial channel length of the transistor 310. Therefore, to achieve a normally-off transistor, it is preferable that the thickness of the third oxide semiconductor layer 408 c be large. Further, when the thickness of the first oxide semiconductor layer 408 a in contact with the gate insulating layer 404 is too large, current might flow through the first oxide semiconductor layer 408 a or an interface thereof. Accordingly, it is preferable that the thickness of the first oxide semiconductor layer 408 a be smaller than that of the second oxide semiconductor layer 408 b, and the thickness of the third oxide semiconductor layer 408 c be larger than or equal to that of the second oxide semiconductor layer 408 b.

For the first to third oxide semiconductor layers 408 a to 408 c, oxide semiconductors which have different constituent elements or oxide semiconductors which have the same constituent elements but whose compositions are different from each other may be used. Note that it is preferable that an oxide semiconductor which has high field-effect mobility be used for the second oxide semiconductor layer 408 b functioning as the channel of the transistor 310.

For example, in the case where the first to third oxide semiconductor layers 408 a to 408 c are formed using oxide semiconductors which contain indium and gallium, an oxide semiconductor in which the indium content is larger than the gallium content is preferably used for the second oxide semiconductor layer 408 b, and oxide semiconductors in which the indium content is lower than or equal to the gallium content are preferably used for the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c.

In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the percentage of indium in the oxide semiconductor is increased, overlaps of the s orbitals are likely to be increased. Accordingly, when the indium content is higher than the gallium content in the second oxide semiconductor layer 408 b, it is possible that the second oxide semiconductor layer 408 b has higher field-effect mobility than an oxide in which the indium content is lower than or equal to the gallium content.

Further, as the ratio of the gallium content to the content of the other metal element(s) becomes higher in a metal oxide, the energy gap of the metal oxide is increased. Accordingly, when the indium content is lower than or equal to the gallium content in the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c, the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c have a larger energy gap than the second oxide semiconductor layer 408 b. The above structure is preferable to effectively form the energy difference between the bottom of the conduction band in the second oxide semiconductor layer 408 b and each of the bottoms of the conduction band in the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c. Further, gallium needs large formation energy of an oxygen vacancy and thus is not likely to generate an oxygen vacancy as compared to indium. Therefore, a metal oxide in which the indium content is lower than or equal to the gallium content has stable characteristics as compared to a metal oxide in which the indium content is higher than the gallium content. Therefore, stabilization on the back channel side in the transistor 310 can be achieved. Note that gallium oxide or zinc gallium oxide may be used for the first oxide semiconductor layer 408 a and/or the third oxide semiconductor layer 408 c.

For example, in the case where an In—Ga—Zn-based oxide semiconductor is used for the first to third oxide semiconductor layers 408 a to 408 c, an In—Ga—Zn-based oxide having any of atomic ratios of In:Ga:Zn=1:1:1 (=⅓:⅓:⅓), In:Ga:Zn=1:3:2 (=⅙: 3/6: 2/6), In:Ga:Zn=2:4:3 (= 2/9: 4/9: 3/9), and In:Ga:Zn=1:5:3 (= 1/9: 5/9: 3/9); or a metal oxide having an atomic ratio which is close to any of the above atomic ratios can be used for the first oxide semiconductor layer 408 a or the third oxide semiconductor layer 408 c. As the second oxide semiconductor layer 408 b, an In—Ga—Zn-based oxide having any of atomic ratios of In:Ga:Zn=3:1:2 (= 3/6:⅙: 2/6), In:Ga:Zn=4:2:3 (= 4/9: 2/9: 3/9), In:Ga:Zn=5:1:3 (= 5/9: 1/9: 3/9), In:Ga:Zn=5:3:4 (= 5/12: 3/12: 4/12), In:Ga:Zn=6:2:4 (= 6/12: 2/12: 4/12), or In:Ga:Zn=7:1:3 (= 7/11: 1/11: 3/11); or a metal oxide having an atomic ratio which is close to any of the above atomic ratios can be used.

Note that for example, the expression “the composition of an oxide including In, Ga, and Zn at the atomic ratio, In:Ga:Zn=a:b:c (a+b+c=1), is in the neighborhood of the composition of an oxide containing In, Ga, and Zn at the atomic ratio, In:Ga:Zn=A:B:C (A+B+C=1)” means that a, b, and c satisfy the following relation: (a−A)²+(b−B)²+(c−C)² r². For example, r may be 0.05.

In this embodiment, an In—Ga—Zn-based oxide having an atomic ratio of In:Ga:Zn=1:3:2 is used as the first oxide semiconductor layer 408 a, an In—Ga—Zn-based oxide having an atomic ratio of In:Ga:Zn=3:1:2 is used as the second oxide semiconductor layer 408 b, and an In—Ga—Zn-based oxide having an atomic ratio of In:Ga:Zn=1:1:1 is used as the third oxide semiconductor layer 408 c.

Note that the oxide semiconductor which is applied to the oxide semiconductor stack 408 is not limited thereto, and a metal oxide which have an appropriate composition in accordance with required electrical characteristics (field-effect mobility, a threshold voltage, variations, and the like) may be used. In order to obtain the needed electrical characteristics, the carrier concentration, the impurity concentration, the defect density, the atomic ratio between a metal element and oxygen, the interatomic distance, the density, and the like are preferably set to appropriate values.

For example, as a stabilizer for reducing variation in electrical characteristics of a transistor, one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr) may be contained instead of gallium (Ga) or in addition to gallium (Ga). As another stabilizer, one or plural kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be contained.

Note that the oxide semiconductor layer can be formed by a sputtering method. Generation of particles in deposition can be prevented by using a sputtering target which contains indium. Therefore, it is preferable to use an oxide semiconductor layer containing indium.

The first to third oxide semiconductor layers 408 a to 408 c have at least one constituent element in common. In this case, depending on materials or deposition conditions of the oxide semiconductor layers, the interfaces between the oxide semiconductor layers are unclear in some cases. Similarly, in the second oxide semiconductor layer 408 b, oxide semiconductors included in the first region 408 b 1 and the second region 408 b 2 have the same constituent elements and the same composition but have different n-type impurity concentrations; therefore, an interface between the regions might be unclear. In FIGS. 2A to 2C, the interface between the first region 408 b 1 and the second region 408 b 2 is schematically denoted by a dotted line, which illustrates the case where the interface is unclear. The same applies to other drawings described below.

An example of a method for manufacturing the transistor 310 is described below with reference to FIGS. 3A to 3E.

First, the gate electrode layer 402 (including a wiring formed using the same layer) is formed over the substrate 400 having an insulating surface.

There is no particular limitation on the substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance high enough to withstand heat treatment performed later. For example, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like can be used. Furthermore, any of these substrates provided with a semiconductor element may be used as the substrate 400. A base insulating layer may be formed over the substrate 400.

The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as a nickel silicide film may be used as the gate electrode layer 402. The gate electrode layer 402 may have either a single-layer structure or a stacked-layer structure. The gate electrode layer 402 may have a tapered shape with a taper angle of greater than or equal to 15° and less than or equal to 70° for example. Here, the taper angle refers to an angle formed between a side surface of a layer having a tapered shape and a bottom surface of the layer.

The material of the gate electrode layer 402 may be a conductive material such as indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide-zinc oxide, or indium tin oxide to which silicon oxide is added.

Alternatively, as the material of the gate electrode layer 402, an In—Ga—Zn-based oxide containing nitrogen, an In—Sn-based oxide containing nitrogen, an In—Ga-based oxide containing nitrogen, an In—Zn-based oxide containing nitrogen, an Sn-based oxide containing nitrogen, an In-based oxide containing nitrogen, or a metal nitride film (such as an indium nitride film, a zinc nitride film, a tantalum nitride film, or a tungsten nitride film) may be used. These materials have a work function of 5 eV or more. Therefore, when the gate electrode layer 402 is formed using any of these materials, the threshold voltage of the transistor can be positive, so that the transistor can be a normally-off switching transistor.

Next, the gate insulating layer 404 is formed so as to cover the gate electrode layer 402 (see FIG. 3A). As the gate insulating layer 404, a single layer or a stack of layers including at least one of the following films formed by a plasma CVD method, a sputtering method, or the like is used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.

Note that in the gate insulating layer 404, a region (the gate insulating layer 404 b in this embodiment) in contact with the first oxide semiconductor layer 408 a to be formed later is preferably an oxide insulating layer, and more preferably has a region containing oxygen in excess of the stoichiometric composition (an oxygen-excess region). In order to provide the oxygen-excess region in the gate insulating layer 404, for example, the gate insulating layer 404 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the formed gate insulating layer 404 to provide the oxygen-excess region. Oxygen can be introduced by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like.

In this embodiment, a silicon nitride film is formed as the gate insulating layer 404 a, and a silicon oxide film is formed as the gate insulating layer 404 b.

Next, an oxide semiconductor film 407 a is formed over the gate insulating layer 404.

The oxide semiconductor film 407 a can be formed by a sputtering method, a molecular beam epitaxy (MBE) method, a CVD method, a pulse laser deposition method, an atomic layer deposition (ALD) method, or the like as appropriate.

The gate insulating layer 404 and the oxide semiconductor film 407 a are preferably formed in succession without exposure to the air. By forming the gate insulating layer 404 and the oxide semiconductor film 407 a in succession without exposure to the air, attachment of hydrogen or a hydrogen compound (e.g., adsorption water) onto a surface of the oxide semiconductor film 407 a can be prevented, and thus mixing of an impurity can be prevented.

A sputtering target which is polycrystalline and has a high relative density (a high filling rate) is used as a sputtering target for forming the oxide semiconductor film. The oxide semiconductor film is formed under the following conditions: the sputtering target in deposition is sufficiently cooled to room temperature; the temperature of a surface of a deposition-target substrate where the oxide semiconductor film is to be formed is increased to room temperature or higher; and an atmosphere in a deposition chamber hardly contains moisture or hydrogen.

The higher density of the sputtering target is more preferable. When the density of the sputtering target is increased, the density of a film to be deposited can also be increased. Specifically, the relative density (filling rate) of the sputtering target is set to be higher than or equal to 90% and lower than or equal to 100%, preferably higher than or equal to 95%, more preferably higher than or equal to 99.9%. Note that the relative density of the sputtering target refers to a ratio of the density of the sputtering target to the density of a material free of porosity having the same composition as the sputtering target.

The sputtering target is preferably sintered in an inert gas atmosphere (a nitrogen atmosphere or a rare gas atmosphere), in vacuum, or in a high-pressure atmosphere. As a sintering method, an atmospheric sintering method, a pressure sintering method, or the like can be used as appropriate. A polycrystalline target obtained by any of these methods is used as a sputtering target. A hot pressing method, a hot isostatic pressing (HIP) method, a discharge plasma sintering method, or an impact method is preferably used as a pressure sintering method. The maximum temperature at which sintering is performed is selected depending on the sintering temperature of the sputtering target material, and it is preferably set to approximately 1000° C. to 2000° C., or more preferably, 1200° C. to 1500° C. The holding time of the maximum temperature is selected depending on the sputtering target material, and 0.5 hours to 3 hours is preferable.

In the case of forming an In—Ga—Zn-based oxide film, a target having an atomic ratio of In:Ga:Zn=3:1:2, a target having an atomic ratio of In:Ga:Zn=1:1:1, or the like is used as the sputtering target. For example, in this embodiment, the oxide semiconductor film 407 a is formed using a target having an atomic ratio of In:Ga:Zn=1:3:2. An oxide semiconductor film 407 b is formed using a target having an atomic ratio of In:Ga:Zn=3:1:2. An oxide semiconductor film 407 c is formed using a target having an atomic ratio of In:Ga:Zn=1:1:1.

To obtain a dense film, it is important to reduce impurities which remain in the deposition chamber. The back pressure (ultimate vacuum: degree of vacuum before introduction of a reaction gas) in the deposition chamber is set to be lower than or equal to 5×10⁻³ Pa, preferably lower than or equal to 6×10⁻⁵ Pa, and the pressure in deposition is set to be lower than 2 Pa, preferably lower than or equal to 0.4 Pa. When the back pressure is set to be low, impurities in the deposition chamber are reduced.

To obtain a dense film, it is also important to reduce impurities contained in a gas that is introduced into the deposition chamber, i.e., a gas used at the deposition. Further, it is important to increase the proportion of oxygen contained in the deposition gas and optimize power. By increasing the proportion of oxygen (the upper limit: 100% oxygen) in the deposition gas and optimizing the power, plasma damage in deposition can be alleviated. Thus, a dense film is easily obtained.

Deposition of the oxide semiconductor film is preferably performed while a quadrupole mass analyzer (hereinafter also referred to as Q-mass) is operated continuously in order that the amount of moisture in the deposition chamber, or the like is monitored by the Q-mass before or in deposition.

For example, in the case where the oxide semiconductor film 407 a is formed by a sputtering method, oxygen or a mixed gas of oxygen and a high-purity rare gas from which impurities such as hydrogen, water, a hydroxyl group, and a hydride have been removed is used as a deposition gas supplied to a deposition chamber of a sputtering apparatus.

Note that heat treatment for dehydration or dehydrogenation may be performed as appropriate on the formed oxide semiconductor film 407 a. Further, oxygen may be supplied to the oxide semiconductor film 407 a which has been subjected to dehydration or dehydrogenation treatment.

Next, the oxide semiconductor film 407 b which contains the n-type impurity and shows variation in concentration of the n-type impurity in the thickness direction is formed on and in contact with the oxide semiconductor film 407 a (see FIG. 3B). The oxide semiconductor film 407 b is preferably deposited in a different deposition chamber from the oxide semiconductor film 407 a. For example, a first region 407 b 1 of the oxide semiconductor film 407 b containing the n-type impurity is deposited by using, as an deposition gas supplied to the deposition chamber, a gas which is obtained by mixing a nitrogen gas or a gas containing nitrogen such as a dinitrogen monoxide gas, with the deposition gas for the oxide semiconductor film 407 a. After that, a flow rate of the nitrogen gas or the gas containing nitrogen such as a dinitrogen monoxide gas is reduced in the same deposition chamber, and a second region 407 b 2 of the oxide semiconductor film 407 b which has a lower n-type impurity concentration than the first region 407 b 1 is formed. The other deposition conditions of the oxide semiconductor film 407 b can be the same as those of the oxide semiconductor film 407 a.

Then, the stack of the oxide semiconductor film 407 a and the oxide semiconductor film 407 b is processed into the island-shaped first and second oxide semiconductor layers 408 a and 408 b by etching treatment using a photolithography method. After that, the oxide semiconductor film 407 c is deposited so as to cover the island-shaped first and second oxide semiconductor layers 408 a and 408 b (see FIG. 3C). The oxide semiconductor film 407 c may be deposited in the same chamber as the oxide semiconductor film 407 a. Deposition conditions of the oxide semiconductor film 407 c can be similar to those of the oxide semiconductor film 407 a.

Next, the oxide semiconductor film 407 c is processed by etching treatment using a photolithography method into the island-shaped third oxide semiconductor layer 408 c, so that the oxide semiconductor stack 408 is formed (see FIG. 3D). The third oxide semiconductor layer 408 c is provided on and in contact with the second oxide semiconductor layer 408 b so as to cover the side surfaces of the first and second oxide semiconductor layers 408 a and 408 b.

Then, a conductive film is formed over the oxide semiconductor stack 408 and processed to form the source electrode layer 410 a and the drain electrode layer 410 b (including a wiring formed using the same layer).

For the source electrode layer 410 a and the drain electrode layer 410 b, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, a metal nitride film containing any of the above elements as a component (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film), or the like can be used, for example. Alternatively, a film of a high-melting-point metal such as Ti, Mo, or W or a metal nitride film of any of these elements (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) may be stacked on one of or both a bottom side and a top side of a metal film of Al, Cu, or the like. Alternatively, the source electrode layer 410 a and the drain electrode layer 410 b may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium oxide-tin oxide (In₂O₃—SnO₂), indium oxide-zinc oxide (In₂O₃—ZnO), or any of these metal oxide materials in which silicon oxide is contained can be used.

For the source electrode layer 410 a and the drain electrode layer 410 b, a metal nitride film such as an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Ga—O film containing nitrogen, an In—Zn—O film containing nitrogen, a Sn—O film containing nitrogen, or an In—0 film containing nitrogen can be used. These films contain the same constituent elements as the oxide semiconductor stack 408 and can therefore stabilize the interface with the oxide semiconductor stack 408.

Next, the insulating layer 412 is formed to cover the source electrode layer 410 a, the drain electrode layer 410 b, and the exposed oxide semiconductor stack 408 (see FIG. 3E).

The insulating layer 412 can be formed using a single layer or a stack of layers of one or more of the following films formed by a plasma CVD method or a sputtering method: a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, a silicon nitride oxide film, and the like. Note that it is preferable that an oxide insulating layer be formed as the insulating layer 412 (in this embodiment, the insulating layer 412 a) in contact with the oxide semiconductor stack 408 because the oxide insulating layer can supply oxygen to the oxide semiconductor stack 408.

For example, a silicon oxide film or a silicon oxynitride film may be formed under the following conditions: the substrate placed in a treatment chamber of a plasma CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., preferably higher than or equal to 200° C. and lower than or equal to 370° C., the pressure in the treatment chamber is greater than or equal to 30 Pa and less than or equal to 250 Pa, preferably greater than or equal to 40 Pa and less than or equal to 200 Pa with introduction of a source gas into the treatment chamber, and high-frequency power is supplied to an electrode provided in the treatment chamber. Under the above conditions, an oxide insulating layer through which oxygen is diffused can be formed.

After the formation of the oxide insulating layer through which oxygen is diffused, a silicon oxide film or a silicon oxynitride film may be formed under the following conditions: the substrate placed in a treatment chamber of the plasma CVD apparatus, which is vacuum-evacuated, without exposure to the air is held at a temperature higher than or equal to 180° C. and lower than or equal to 250° C., preferably higher than or equal to 180° C. and lower than or equal to 230° C., the pressure in the treatment chamber is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa with introduction of a source gas into the treatment chamber, and high-frequency power higher than or equal to 0.17 W/cm² and lower than or equal to 0.5 W/cm², preferably higher than or equal to 0.26 W/cm² and lower than or equal to 0.35 W/cm² is supplied to an electrode provided in the treatment chamber. Under the above conditions, the decomposition efficiency of the source gas in plasma is enhanced, oxygen radicals are increased, and oxidation of the source gas is promoted; thus, the oxygen content in the formed silicon oxide film or silicon oxynitride film is in excess of that in the stoichiometric composition. However, the bonding strength of silicon and oxygen is weak in the above substrate temperature range; therefore, part of oxygen is released by heating. Thus, it is possible to form an oxide insulating layer which contains oxygen in a proportion higher than that of oxygen in the stoichiometric composition and from which part of oxygen is released by heating.

In this embodiment, a stack of the silicon oxide film through which oxygen is diffused and the silicon oxide film from which part of oxygen is released by heating, which are described above, is formed as the insulating layer 412 a, and a silicon nitride film is formed as the insulating layer 412 b.

The structure of this embodiment includes oxide insulating layers (specifically silicon oxide films) as the insulating layers (the gate insulating layer 404 b and the insulating layer 412 a) in contact with the oxide semiconductor stack 408. Therefore, it is possible to supply oxygen to the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c, so that oxygen vacancies in the oxide semiconductor layers can be filled. In addition, silicon nitride films are provided as the insulating layers (the gate insulating layer 404 a and the insulating layer 412 b) which are provided above and below the oxide semiconductor stack 408 to be in contact with the oxide insulating layers. The silicon nitride films each can function as a blocking film which prevents hydrogen or a compound containing hydrogen (e.g., water) from entering the oxide semiconductor stack 408. Accordingly, with such a stacked-layer structure, the reliability of the transistor can be improved.

Heat treatment may be performed after the insulating layer 412 is formed. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., more preferably higher than or equal to 300° C. and lower than or equal to 450° C.

Through the above steps, the transistor 310 of this embodiment can be formed.

In the transistor described in this embodiment, the second oxide semiconductor layer 408 b which functions as a main current path (channel) of the transistor is sandwiched between the first oxide semiconductor layer 408 a and the third oxide semiconductor layer 408 c which have lower carrier densities than the second oxide semiconductor layer 408 b. In this structure, the channel can be separated from the interface with the insulating layer in contact with the oxide semiconductor stack 408, i.e., a buried channel can be formed; thus, the field-effect mobility of the transistor can be improved.

Further, this structure prevents formation of a trap level at the interface of the second oxide semiconductor layer 408 b functioning as the channel, and thus enables the transistor to have high reliability.

Further, the first region 408 b 1, which is provided on the gate insulating layer side of the second oxide semiconductor layer 408 b functioning as the channel, contains the n-type impurity at a higher concentration than the second region 408 b 2, which is provided on the back channel side, whereby off-state current can be controlled while the on-state characteristics (e.g., on-state current and field-effect mobility) of the transistor are improved.

The methods and structures described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.

Embodiment 2

In this embodiment, an example of a method for manufacturing a semiconductor device which is different from that described in Embodiment 1 is described with reference to FIGS. 10A to 10E. Embodiment 1 can be applied to the same portions as Embodiment 1 or portions having functions similar to those of Embodiment 1, and therefore, description thereof is not omitted. In addition, detailed description of the same portions is not repeated.

First, in a manner similar to the process illustrated in FIGS. 3A to 3C, the gate insulating layer 404 including the gate insulating layer 404 a and the gate insulating layer 404 b is formed over the substrate 400, the island-shaped first oxide semiconductor layer 408 a and the island-shaped second oxide semiconductor layer 408 b are formed over the gate insulating layer 404, and the oxide semiconductor film 407 c is formed to cover the first oxide semiconductor layer 408 a and the second oxide semiconductor layer 408 b.

Then, a conductive film 411 to be the source electrode layer 410 a and the drain electrode layer 410 b (including a wiring formed using the same layer) is formed over the oxide semiconductor film 407 c.

After the formation of the conductive film 411, a resist mask 460 is formed (see FIG. 10A). The resist mask 460 in this embodiment has a depressed portion or a projecting portion. In other words, the resist mask 460 can be referred to as a resist mask having a plurality of regions (here, two regions) with different thicknesses. A thick region of the resist mask 460 is referred to as a projecting portion of the resist mask 460. A thin region of the resist mask 460 is referred to as a depressed portion of the resist mask 460.

The projecting portion of the resist mask 460 is formed over regions where the source electrode layer 410 a and the drain electrode layer 410 b are to be formed later, and the depressed portion of the resist mask 460 is formed in a region which is to be a channel region that is positioned between the source electrode layer 410 a and the drain electrode layer 410 b.

The resist mask 460 can be formed using a multi-tone mask. A multi-tone mask is a mask capable of light exposure with multi-level light quantity, typically, light exposure with three levels of light quantity to provide an exposed region, a half-exposed region, and an unexposed region. When a multi-tone mask is used, one-time light exposure and development process allows a resist mask with plural thicknesses (typically, two kinds of thicknesses) to be formed. Therefore, by the usage of a multi-tone mask, the number of photomasks can be reduced.

By light exposure using the multi-tone mask and development, the resist mask 460 which includes regions having different thicknesses can be formed. Note that this embodiment is not limited thereto, and the resist mask 460 may be formed without a multi-tone mask.

Next, the conductive film 411 and the oxide semiconductor film 407 c are selectively etched at the same time with the use of the resist mask 460, so that an oxide semiconductor layer 418 c which is an island-shaped oxide semiconductor layer and a conductive layer 410 are formed (see FIG. 10B).

Then, the resist mask 460 is made to recede (made smaller), so that a resist mask 462 a and a resist mask 462 b are formed (see FIG. 10C). In order to make the resist mask 460 recede (smaller), ashing using oxygen plasma, or the like, may be performed. The resist mask 460 is made to recede (made smaller), so that a portion of the conductive layer 410 which is positioned between the resist mask 462 a and the resist mask 462 b and the periphery of the conductive layer 410 are exposed.

Next, a region of the conductive layer 410 which is exposed between the resist mask 462 a and the resist mask 462 b is selectively etched, so that the source electrode layer 410 a, the drain electrode layer 410 b, and a third oxide semiconductor layer 428 c are formed (see FIG. 10D).

Note that as illustrated in FIG. 10D, by the etching using the resist mask 462 a and the resist mask 462 b, which are obtained by making the resist mask 460 recede (smaller), thin regions are formed in the periphery of the third oxide semiconductor layer 428 c which covers the first oxide semiconductor layer 408 a and the second oxide semiconductor layer 408 b and in a region between the source electrode layer 410 a and the drain electrode layer 410 b. That is, the end portion of the third oxide semiconductor layer 428 c sticks out beyond the end portion of the source electrode layer 410 a or the drain electrode layer 410 b. Note that in the third oxide semiconductor layer 428 c, the periphery and a region below a groove portion (depressed portion) between the source electrode layer 410 a and the drain electrode layer 410 b have the same thickness.

Then, in a manner similar to the step illustrated in FIG. 3E, the insulating layer 412 including the insulating layer 412 a and the insulating layer 412 b is formed over the source electrode layer 410 a and the drain electrode layer 410 b (see FIG. 10E).

In the above manner, a transistor 320 of this embodiment can be formed.

By application of the method for manufacturing the transistor described in this embodiment, the number of light exposure masks for forming the oxide semiconductor stack can be reduced and the number of photolithography steps corresponding to the number of light exposure masks can also be reduced; therefore, simplification in the process and a reduction in the manufacturing cost can be achieved.

The methods and structures described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.

Embodiment 3

In this embodiment, a semiconductor device having a different structure from the semiconductor device described in Embodiment 1 or 2 and a method for manufacturing the semiconductor device are described with reference to FIG. 12, FIGS. 16A to 16C, and FIGS. 17A to 17D. In this embodiment, a bottom-gate transistor is described as an example of the semiconductor device. Embodiment 1 or 2 can be applied to the same portions as Embodiment 1 or 2 or portions having functions similar to those of Embodiment 1 or 2; therefore, repetitive description thereof is omitted. In addition, detailed description of the same portions is not repeated.

FIGS. 16A to 16C illustrate a structural example of a transistor 330. FIG. 16A is a plan view of the transistor 330, FIG. 16B is a cross-sectional view taken along X2-Y2 in FIG. 16A, and FIG. 16C is a cross-sectional view taken along V2-W2 in FIG. 16A.

The transistor 330 illustrated in FIGS. 16A to 16C is similar to the transistor 310 illustrated in FIGS. 2A to 2C in that the gate electrode layer 402 which is provided over the substrate 400 having an insulating surface, the gate insulating layer 404 over the gate electrode layer 402, an oxide semiconductor stack which is on and in contact with the gate insulating layer 404 and overlaps with the gate electrode layer 402, and the source electrode layer 410 a and the drain electrode layer 410 b which are electrically connected to the oxide semiconductor stack are included. Further, the insulating layer 412 which covers the source electrode layer 410 a and the drain electrode layer 410 b and is in contact with the oxide semiconductor stack may be included in the transistor 330 as a component.

A difference between the transistor 330 in FIGS. 16A to 16C and the transistor 310 in FIGS. 2A to 2C is positions where the oxide semiconductor stack is connected to the source electrode layer 410 a and the drain electrode layer 410 b. That is, in the transistor 310, the source electrode layer 410 a and the drain electrode layer 410 b are formed after the oxide semiconductor stack 408 is formed, whereby at least part of a top surface of the oxide semiconductor stack 408 is in contact with the source electrode layer 410 a and the drain electrode layer 410 b. Meanwhile, in the transistor 330, the oxide semiconductor stack is formed after the source electrode layer 410 a and the drain electrode layer 410 b are formed, whereby at least part of a top surface of the source electrode layer 410 a and part of a top surface of the drain electrode layer 410 b are in contact with the oxide semiconductor stack 438.

In the transistor 330, the oxide semiconductor stack 438 includes a first oxide semiconductor layer 438 a which is in contact with the source electrode layer 410 a, the drain electrode layer 410 b, and the gate insulating layer 404; a second oxide semiconductor layer 438 b which is on and in contact with the first oxide semiconductor layer 438 a; and a third oxide semiconductor layer 438 c which is on and in contact with the second oxide semiconductor layer 438 b. As the second oxide semiconductor layer 438 b included in the oxide semiconductor stack 438, an oxide semiconductor layer containing an impurity imparting n-type conductivity (n-type impurity) is used. The second oxide semiconductor layer 438 b shows variation in concentration of the n-type impurity in the thickness direction. In the second oxide semiconductor layer 438 b, a first region 438 b 1 which is in contact with the first oxide semiconductor layer 438 a contains the n-type impurity at a higher concentration than a region in contact with the third oxide semiconductor layer 438 c.

An example of a method for manufacturing the transistor 330 is described below with reference to FIGS. 17A to 17D.

First, in a manner similar to the step illustrated in FIG. 3A, the gate electrode layer 402 and the gate insulating layer 404 (the gate insulating layer 404 a and the gate insulating layer 404 b) are formed over the substrate 400. After that, a conductive film is formed over the gate insulating layer 404 and then processed to form the source electrode layer 410 a and the drain electrode layer 410 b (including a wiring formed using the same layer) (see FIG. 17A).

Next, an oxide semiconductor film 437 a is formed over the gate insulating layer 404 to be in contact with the source electrode layer 410 a and the drain electrode layer 410 b. The oxide semiconductor film 437 a can be formed using a material and a method similar to those for the oxide semiconductor film 407 a described in Embodiment 1.

Next, an oxide semiconductor film 437 b which contains the n-type impurity and shows variation in concentration of the n-type impurity in the thickness direction is formed on and in contact with the oxide semiconductor film 437 a. The oxide semiconductor film 437 b can be formed using a material and method similar to those of the oxide semiconductor film 407 b described in Embodiment 1.

After that, an oxide semiconductor film 437 c is deposited to be on and in contact with the oxide semiconductor film 437 b (see FIG. 17B). The oxide semiconductor film 437 c may be deposited using the same deposition chamber as the oxide semiconductor film 437 a. Deposition conditions of the oxide semiconductor film 437 c can be similar to those of the oxide semiconductor film 407 a.

In the case where steps for stacking the oxide semiconductor film 437 a, the oxide semiconductor film 437 b and the oxide semiconductor film 437 c in this order are performed successively without exposure to the air, a manufacturing apparatus a top view of which is illustrated in FIG. 12 may be used.

The manufacturing apparatus illustrated in FIG. 12 is single wafer multi-chamber equipment, which includes three sputtering devices 10 a, 10 b, and 10 c, a substrate supply chamber 11 provided with three cassette ports 14 for holding a process substrate, load lock chambers 12 a and 12 b, a transfer chamber 13, a substrate heating chamber 15, and the like. Note that a transfer robot for transferring a substrate to be treated is provided in each of the substrate supply chamber 11 and the transfer chamber 13. The atmospheres of the sputtering devices 10 a, 10 b, and 10 c, the transfer chamber 13, and the substrate heating chamber 15 are preferably controlled so as to hardly contain hydrogen and moisture (i.e., as an inert atmosphere, a reduced pressure atmosphere, or a dry air atmosphere). For example, a preferable atmosphere is a dry nitrogen atmosphere in which the dew point of moisture is −40° C. or lower, preferably −50° C. or lower. An example of a procedure of the manufacturing steps with use of the manufacturing apparatus illustrated in FIG. 12 is as follows. The process substrate is transferred from the substrate supply chamber 11 to the substrate heating chamber 15 through the load lock chamber 12 a and the transfer chamber 13; moisture attached to the process substrate is removed by vacuum baking in the substrate heating chamber 15; the process substrate is transferred to the sputtering device 10 c through the transfer chamber 13; and the oxide semiconductor film 437 a is deposited in the sputtering device 10 c. Then, the process substrate is transferred to the sputtering device 10 a through the transfer chamber 13 without exposure to air, and the oxide semiconductor film 437 b is deposited in the sputtering device 10 a. Then, the process substrate is transferred to the sputtering device 10 b through the transfer chamber 13 without exposure to air, and the oxide semiconductor film 437 c is deposited in the sputtering device 10 b. If needed, the process substrate is transferred to the substrate heating chamber 15 through the transfer chamber 13 without exposure to air and heat treatment is performed. As described above, with use of the manufacturing apparatus illustrated in FIG. 12, a manufacturing process can proceed without exposure to air. Further, with of the sputtering devices in the manufacturing apparatus in FIG. 12, a process performed without exposure to the air can be achieved by change of the sputtering target.

Next, the oxide semiconductor films 437 a to 437 c are processed into the first to third oxide semiconductor layers 438 a to 438 c having island shapes by etching treatment using a photolithography method, so that the oxide semiconductor stack 438 is formed (see FIG. 17C).

In this embodiment, the oxide semiconductor films 437 a to 437 c are processed into island shapes by one etching treatment; thus, end portions of the oxide semiconductor layers included in the oxide semiconductor stack 438 are aligned with each other. Note that in this specification, “aligning with” includes “substantially aligning with”. For example, an end portion of a layer A and an end portion of a layer B, which are included in a stacked-layer structure etched using the same mask, are considered to be aligned with each other.

Then, in a manner similar to the step illustrated in FIG. 3E, the insulating layer 412 including the insulating layer 412 a and the insulating layer 412 b is formed over the oxide semiconductor stack 438, the source electrode layer 410 a, and the drain electrode layer 410 b (see FIG. 17D).

In the above manner, the transistor 330 in this embodiment can be formed.

In the transistor described in this embodiment, the second oxide semiconductor layer functioning as a main current path (channel) and containing the n-type impurity is sandwiched between the first and the third oxide semiconductor layers which have lower conductivity than the second oxide semiconductor layer. In the second oxide semiconductor layer, a region on the channel side contains the n-type impurity at a higher concentration than a region on the back channel side. Accordingly, the transistor described in this embodiment is a buried channel transistor in which the current path is separated from an interface of an insulating layer and thus has high field-effect mobility. In addition, the transistor is a highly reliable transistor in which influence of an interface state which might be formed on the back channel side is reduced and photodegradation (e.g., negative-bias temperature stress photodegradation) is reduced.

Further, this structure prevents formation of a trap level at the interface of the second oxide semiconductor layer 438 b functioning as the channel, and thus enables the transistor to have high reliability. In the second oxide semiconductor layer 438 b functioning as the channel, the first region 438 b 1 provided on the gate insulating layer side contains the n-type impurity at a higher concentration than a second region 438 b 2 provided on the back channel side; therefore, the off-state current can be controlled while the on-state characteristics (e.g., on-state current and field-effect mobility) of the transistor are improved.

Further, since the oxide semiconductor stack is processed by one time etching treatment, the number of light exposure masks used for processing the oxide semiconductor stack can be reduced, and the number of photolithography steps corresponding to the number of light exposure masks can also be reduced; thus, simplification in the process and a reduction in the manufacturing cost can be achieved.

The methods and structures described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments.

Embodiment 4

In this embodiment, an example of a semiconductor layer applicable to the transistors of Embodiments 1 to 3 is described in detail with reference to drawings.

An oxide semiconductor layer is classified roughly into a single-crystal oxide semiconductor layer and a non-single-crystal oxide semiconductor layer. The non-single-crystal oxide semiconductor layer includes any of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, and the like.

The amorphous oxide semiconductor layer has disordered atomic arrangement and no crystalline component. A typical example thereof is an oxide semiconductor layer in which no crystal part exists even in a microscopic region, and the whole of the layer is amorphous.

The microcrystalline oxide semiconductor layer includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Thus, the microcrystalline oxide semiconductor layer has a higher degree of atomic order than the amorphous oxide semiconductor layer. Hence, the density of defect states of the microcrystalline oxide semiconductor layer is lower than that of the amorphous oxide semiconductor layer.

The CAAC-OS film is one of oxide semiconductor layers including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor layer. The CAAC-OS film is described in detail below.

In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.

According to the TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film.

On the other hand, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.

From the results of the cross-sectional TEM image and the plan TEM image, alignment is found in the crystal parts in the CAAC-OS film.

A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when the CAAC-OS film including an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (219) is around 31°. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO₄ crystal. Here, analysis (Φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (0 axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor layer of InGaZnO₄, six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when Φ scan is performed with 2θ fixed at around 56°.

According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are different between crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.

Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, for example, in the case where a shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.

Further, the degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions.

Note that when the CAAC-OS film with an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak of 2θ appear at around 31° and a peak of 2θ do not appear at around 36°.

In a transistor using the CAAC-OS film, a change in electric characteristics due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability.

Note that an oxide semiconductor layer may be a stacked film including two or more films of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, and a CAAC-OS film, for example.

An example of a deposition model of the CAAC-OS film is described below. Note that the following model is just a consideration.

During deposition, fine sputtered particles fly from a target, and a film is formed such that the sputtered particles adhere onto the deposition-target substrate. When the temperature of the substrate is higher than or equal to 200° C., the sputtered particles are rearranged because the substrate is heated. Thus, a dense film is formed.

When ions collide with a surface of a sputtering target, a crystal region included in the sputtering target is cleaved along an a-b plane, and sputtered particles whose top and bottom surfaces are each aligned with a layer parallel to the a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) are separated from the sputtering target. On the assumption that a crystal particle which is sputtered from the surface of a sputtering target 2002 and released is a flat-plate-like sputtered particle 2001 having c-axis alignment as illustrated in FIG. 13A, deposition can be schematically illustrated by a model diagram in FIG. 13B. The outermost surface of the flat-plate-like sputtered particle is preferably a (Ga or Zn)O plane as illustrated in FIG. 13C.

In deposition, when the oxygen flow rate is high and the pressure inside a chamber 2003 is high, oxygen ions are attached to the flat-plate-like sputtered particle as illustrated in FIG. 14A, so that the flat-plate-like sputtered particle can have much oxygen on its surface. Another flat-plate-like sputtered particle is stacked thereover before the attached oxygen is released; thus, much oxygen can be contained in the film as illustrated in FIG. 15C. This adsorbed oxygen contributes to a reduction in oxygen vacancies in the oxide semiconductor.

To form an oxide semiconductor film including a crystal region with c-axis alignment, the substrate temperature in film formation is preferably increased. However, when the substrate temperature is higher than 350° C., the adsorbed oxygen might be released as illustrated in FIG. 14B. Accordingly, the substrate temperature is set to be higher than or equal to 150° C. and lower than or equal to 350° C., preferably higher than or equal to 160° C. and lower than or equal to 230° C., and an oxygen gas is used alone as the deposition gas, whereby an oxide semiconductor film including a crystal region with c-axis alignment, i.e., a CAAC-OS film can be formed.

FIG. 15A illustrates a model of a process in which one flat-plate-like sputtered particle reaches the surface of a substrate 2000 and is stabilized in deposition. As illustrated in FIG. 15A, the flat-plate-like sputtered particle reaches the substrate surface with its crystalline state maintained; thus, a CAAC-OS film is likely to be formed. Further, flat-plate-like sputtered particles are stacked as illustrated in FIG. 15B; thus, a CAAC-OS film is likely to be formed. Note that a CAAC-OS film is a film which contains much oxygen as illustrated in FIG. 15C and in which oxygen vacancies are reduced.

In the CAAC-OS film over the substrate 2000, a series of about 2 to 20 indium atoms exist in a lateral direction to form a layer including indium atoms. Note that in some cases, the layer has a series of 20 or more indium atoms; for example, the layer may have a series of 2 to 50 indium atoms, 2 to 100 indium atoms, or 2 to 500 indium atoms in a lateral direction.

Layers including indium atoms overlap with each other. The number of layers is greater than or equal to 1 and less than or equal to 20, greater than or equal to 1 and less than or equal to 10, or greater than or equal to 1 and less than or equal to 4.

As described above, a stack of the layers including indium atoms often appears to be a cluster including several indium atoms in a lateral direction and several layers in a longitudinal direction. This is because each of the sputtered particles has a flat-plate-like shape.

By increasing the temperature of the deposition-target substrate, migration of sputtered particles is likely to occur on a substrate surface. With this effect, a flat-plate-like sputtered particle reaches the substrate surface, moves slightly, and then is attached to the substrate surface with a flat plane (a-b plane) of the sputtered particle facing toward the substrate surface. Therefore, an oxide semiconductor film having a crystal region which is c-axis-aligned perpendicularly to the surface of the oxide semiconductor film is easily formed.

Further, heat treatment at a temperature higher than or equal to 200° C. may be performed after the deposition of the oxide semiconductor film, so that a denser film is obtained. However, in that case, oxygen vacancies might be generated when impurity elements (e.g., hydrogen and water) in the oxide semiconductor film are reduced. Therefore, before the heat treatment is performed, an insulating layer containing excess oxygen is preferably provided over or below the oxide semiconductor film, in which case oxygen vacancies in the oxide semiconductor film can be reduced by the heat treatment.

An oxide semiconductor film shortly after deposition is made dense; thus, a dense film which is thin and close to single crystal can be obtained. Since oxygen, hydrogen, or the like hardly diffuses within the film, a semiconductor device including the dense oxide semiconductor film can achieve improvement in reliability.

In an oxide semiconductor stack included in a transistor of one embodiment of the present invention, first to third oxide semiconductor layers may have either an amorphous structure or a crystalline structure. Note that a CAAC-OS film is preferably used as the second oxide semiconductor layer functioning as a channel, in which case the density of states (DOS) attributed to an oxygen vacancy in the second oxide semiconductor layer can be reduced.

In the case where the second oxide semiconductor layer and the third oxide semiconductor layer which is formed on and in contact with the second oxide semiconductor layer are both CAAC-OS films, the crystal structure is preferably continuous between the second oxide semiconductor layer and the third oxide semiconductor layer. When the third oxide semiconductor layer is continuous with the second oxide semiconductor layer in terms of crystal structure, DOS is less likely to be formed at the interface between the two layers.

Note that all of the first to third oxide semiconductor layers may have an amorphous structure or may be CAAC-OS films. Note that as described above, when the first oxide semiconductor layer in contact with the gate insulating layer contains the constituent element of the gate insulating layer as an impurity, the crystallinity of the first oxide semiconductor layer might be reduced. Here, when the thickness of the first oxide semiconductor layer is greater than or equal to 3 nm and less than or equal to 20 nm, preferably greater than or equal to 5 nm and less than or equal to 10 nm, even when the crystallinity of part of the first oxide semiconductor layer is reduced owing to the impurity, influence upon the second oxide semiconductor layer can be reduced, so that the whole second oxide semiconductor layer including its interface with the first oxide semiconductor layer can be a CAAC-OS film.

The oxide semiconductor layer described in this embodiment can be applied to the semiconductor devices in Embodiments 1 to 3.

Embodiment 5

A semiconductor device having a display function (also referred to as a display device) can be manufactured using any of the transistors described in Embodiments 1 to 3. Further, part or all of the driver circuitry which includes the transistor can be formed over a substrate where a pixel portion is formed, whereby a system-on-panel can be formed.

In FIG. 4A, a sealant 4005 is provided so as to surround a pixel portion 4002 provided over a substrate 4001, and the pixel portion 4002 is sealed with a substrate 4006. In FIG. 4A, a scan line driver circuit 4004 and a signal line driver circuit 4003 which are each formed using a single crystal semiconductor film or a polycrystalline semiconductor film over an IC chip or a substrate separately prepared are mounted on the substrate 4001, in a region that is different from the region surrounded by the sealant 4005. Various signals and potentials are supplied to the pixel portion 4002 through the signal line driver circuit 4003 and the scan line driver circuit 4004 from flexible printed circuits (FPCs) 4018 a and 4018 b.

In FIGS. 4B and 4C, the sealant 4005 is provided to surround the pixel portion 4002 and the scan line driver circuit 4004 which are provided over the substrate 4001. The substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Consequently, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with a display element by the substrate 4001, the sealant 4005, and the substrate 4006. In FIGS. 4B and 4C, the signal line driver circuit 4003 which is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over an IC chip or a substrate separately prepared is mounted on the substrate 4001, in a region that is different from the region surrounded by the sealant 4005. In FIGS. 4B and 4C, various signals and potentials are supplied to the pixel portion 4002 through the signal line driver circuit 4003 and the scan line driver circuit 4004 from an FPC 4018.

Although FIGS. 4B and 4C each illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the substrate 4001, one embodiment of the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

Note that a connection method of a separately formed driver circuit is not particularly limited, and a chip on glass (COG) method, a wire bonding method, a tape automated bonding (TAB) method, or the like can be used. FIG. 4A shows an example in which the signal line driver circuit 4003 and the scan line driver circuit 4004 are mounted by a COG method. FIG. 4B shows an example in which the signal line driver circuit 4003 is mounted by a COG method. FIG. 4C shows an example in which the signal line driver circuit 4003 is mounted by a TAB method.

Note that the display device includes in its category a panel in which the display element is sealed, and a module in which an IC including a controller or the like is mounted on the panel. Specifically, a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Furthermore, the display device also includes the following modules in its category: a module to which a connector such as an FPC or a TCP is attached; a module having a TCP at the tip of which a printed wiring board is provided; and a module in which an integrated circuit (IC) is directly mounted on a display element by a COG method.

The pixel portion and the scan line driver circuit provided over the substrate include a plurality of transistors, and the transistor described in Embodiment 1 or Embodiment 2 can be applied thereto.

As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic electroluminescent (EL) element, an organic EL element, and the like. Furthermore, a display medium whose contrast is changed by an electric effect, such as an electronic ink display device (electronic paper), can be used.

Embodiments of the semiconductor device are described with reference to FIGS. 4A to 4C and FIGS. 5A and 5B. FIGS. 5A and 5B correspond to cross-sectional views along line M-N in FIG. 4B. Examples of a liquid crystal display device using a liquid crystal element as a display element are illustrated in FIGS. 5A and 5B.

A liquid crystal display device can employ a vertical electric field mode or a horizontal electric field mode. FIG. 5A illustrates an example in which a vertical electric field mode is employed, and FIG. 5B illustrates and example in which a fringe field switching (FFS) mode, which is one of horizontal electric field modes, is employed.

Note that a transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element to form a display panel. A variety of display elements can be used as the display element as long as display can be performed.

As illustrated in FIGS. 4A to 4C and FIGS. 5A and 5B, the semiconductor device includes a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are electrically connected to a terminal included in the FPC 4018 or 4018 b through an anisotropic conductive layer 4019.

The connection terminal electrode 4015 is formed from the same conductive layer as a first electrode layer 4034. The terminal electrode 4016 is formed from the same conductive layer as gate electrode layers of the transistor 4010 and a transistor 4011.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the substrate 4001 include a plurality of transistors. FIGS. 5A and 5B illustrate the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scan line driver circuit 4004. In FIGS. 5A and 5B, insulating layers 4032 a and 4032 b are provided over the transistors 4010 and 4011.

In FIG. 5B, a planarization insulating layer 4040 is provided over the insulating layer 4032 b, and an insulating layer 4042 is provided between the first electrode layer 4034 and the second electrode layer 4031.

Any of the transistors described in Embodiments 1 to 3 can be applied to the transistor 4010 and the transistor 4011. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 310 described in Embodiment 1 is used is described. The transistors 4010 and 4011 are bottom-gate transistors.

The transistors 4010 and 4011 each include a stacked-layer structure of a gate insulating layers 4020 a and 4020 b. In FIG. 5A, the gate insulating layers 4020 a and 4020 b of the transistors 4010 and 4011 and the insulating layers 4032 a and 4032 b provided over the transistors 4010 and 4011 extend below the sealant 4005 to cover an end portion of the connection terminal electrode 4015. In FIG. 5B, the gate insulating layer 4020 a and the insulating layer 4032 b extend below the sealant 4005 to cover the end portion of the connection terminal electrode 4015, and the insulating layer 4032 b covers side surfaces of the gate insulating layer 4020 b and the insulating layer 4032 a. It is preferable to apply of a film (e.g., a silicon nitride film) having a blocking property against hydrogen or a compound containing hydrogen (e.g., water) to each of the gate insulating layer 4020 a and the insulating layer 4032 b because the film can prevent the entry of hydrogen or a compound containing hydrogen from the air or the like, resulting in an improvement in the reliability of the semiconductor device.

In each of the transistors 4010 and 4011, a second oxide semiconductor layer which functions as a current path (channel) and contains an n-type impurity is sandwiched between first and third oxide semiconductor layers which have lower conductivity than the second oxide semiconductor layer. In the second oxide semiconductor layer, a region on the channel side contains the n-type impurity at a higher concentration than a region on the back channel side. Accordingly, each of the transistors 4010 and 4011 is a buried-channel transistor in which a current path is separated from the interface with the insulating layer, and therefore has high field-effect mobility. In addition, each of the transistors 4010 and 4011 is a highly reliable transistor in which influence of an interface state which might be formed on the back channel side is reduced and photodegradation (e.g., negative-bias temperature stress photodegradation) is reduced.

Moreover, a conductive layer may be provided so as to overlap with a channel formation region in the oxide semiconductor layer of the transistor 4011 for the driver circuit. When the conductive layer is provided so as to overlap with the channel formation region in the oxide semiconductor layer, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. The conductive layer may have the same potential as or a potential different from that of a gate electrode layer of the transistor 4011, and can function as a second gate electrode layer. The potential of the conductive layer may be in a floating state, for example.

In addition, the conductive layer has a function of blocking an external electric field, that is, a function of preventing an external electric field (particularly, a function of preventing static electricity) from affecting the inside (a circuit portion including a transistor). A blocking function of the conductive layer can prevent variation in the electrical characteristics of the transistor due to an influence of an external electric field such as static electricity.

In FIGS. 5A and 5B, a liquid crystal element 4013 includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4033 and 4038 functioning as alignment films are provided so that the liquid crystal layer 4008 is positioned therebetween.

In FIG. 5A, the second electrode layer 4031 is provided on the substrate 4006 side, and the first electrode layer 4034 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 provided therebetween. In FIG. 5B, the second electrode layer 4031 having an opening pattern is provided below the liquid crystal layer 4008, and the first electrode layer 4034 having a flat plate shape is provided below the second electrode layer 4031 with the insulating layer 4042 provided therebetween. In FIG. 5B, the second electrode layer 4031 having an opening pattern includes a bent portion or a comb-shaped portion. The first electrode layer 4034 and the second electrode layer 4031 do not have the same shape or do not overlap with each other in order to generate an electric field between the electrodes. Note that a structure may be employed in which the second electrode layer 4031 having a flat plate shape is formed on and in contact with the planarization insulating layer 4040, and the first electrode layer 4034 having an opening pattern and serving as a pixel electrode is formed over the second electrode layer 4031 with the insulating layer 4042 provided therebetween.

The first electrode layer 4034 and the second electrode layer 4031 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or graphene.

Alternatively, the first electrode layer 4034 and the second electrode layer 4031 can be formed using one or more materials selected from metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag); an alloy of any of these metals; and a nitride of any of these metals.

A conductive composition containing a conductive high molecule (also referred to as a conductive polymer) can be used for the first electrode layer 4034 and the second electrode layer 4031. As the conductive high molecule, what is called a π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

A spacer 4035 is a columnar spacer obtained by selective etching of an insulating layer and is provided in order to control the thickness of the liquid crystal layer 4008 (a cell gap). Alternatively, a spherical spacer may be used.

In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. These liquid crystal materials may be a low molecular compound or a high molecular compound. Such a liquid crystal material (liquid crystal composition) exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.

Alternatively, a liquid crystal composition exhibiting a blue phase for which an alignment film is unnecessary may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008 is in contact with the first electrode layer 4034 and the second electrode layer 4031. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. The blue phase can be exhibited using a liquid crystal composition which is a mixture of a liquid crystal and a chiral material. In order to increase the temperature range where the blue phase is exhibited, a liquid crystal layer may be formed by adding a polymerizable monomer, a polymerization initiator, and the like to a liquid crystal composition exhibiting a blue phase and by performing polymer stabilization treatment. The liquid crystal composition exhibiting a blue phase has a short response time, and has optical isotropy, which contributes to the exclusion of the alignment process and reduction of viewing angle dependence. In addition, since an alignment film does not need to be provided and rubbing treatment is unnecessary, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device can be reduced in the manufacturing process. Thus, productivity of the liquid crystal display device can be increased.

The specific resistivity of the liquid crystal material is greater than or equal to 1×10⁹ Ω·cm, preferably greater than or equal to 1×10¹¹ Ω·cm, more preferably greater than or equal to 1×10¹² Ω·cm. Note that the specific resistivity in this specification is measured at 20° C.

The size of a storage capacitor formed in the liquid crystal display device is set considering the leakage current of the transistor provided in the pixel portion or the like so that charge can be held for a predetermined period. The size of the storage capacitor may be set considering the off-state current of a transistor or the like. By using a transistor including an oxide semiconductor layer, which is disclosed in this specification, it is enough to provide a storage capacitor having a capacitance that is ⅓ or less, preferably ⅕ or less of liquid crystal capacitance of each pixel.

In the transistor including an oxide semiconductor layer, which is disclosed in this specification, the current in an off state (off-state current) can be made small. Accordingly, an electric signal such as an image signal can be held for a longer period and a writing interval can be set longer. Accordingly, the frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption.

The transistor including an oxide semiconductor layer, which is disclosed in this specification, can have high field-effect mobility; thus, the transistor can operate at high speed. For example, when such a transistor is used for a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor in a driver circuit portion can be formed over one substrate. In addition, by using such a transistor in a pixel portion, a high-quality image can be provided.

For the liquid crystal display device, a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, or the like can be used.

A normally black liquid crystal display device such as a transmissive liquid crystal display device utilizing a vertical alignment (VA) mode may be used. Some examples are given as the vertical alignment mode. For example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, or an advanced super view (ASV) mode can be used. Furthermore, this embodiment can be applied to a VA liquid crystal display device. The VA liquid crystal display device has a kind of form in which alignment of liquid crystal molecules of a liquid crystal display panel is controlled. In the VA liquid crystal display device, liquid crystal molecules are aligned in a vertical direction with respect to a panel surface when no voltage is applied. Moreover, it is possible to use a method called domain multiplication or multi-domain design, in which a pixel is divided into some regions (subpixels) and molecules are aligned in different directions in their respective regions.

In the display device, a black matrix (a light-blocking layer), an optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, and the like are provided as appropriate. For example, circular polarization may be obtained by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source.

As a display method in the pixel portion, a progressive method, an interlace method or the like can be employed. Further, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, R, G, B, and W (W corresponds to white); R, G, B, and one or more of yellow, cyan, magenta, and the like; or the like can be used. Further, the sizes of display regions may be different between respective dots of color elements. Note that one embodiment of the disclosed invention is not limited to the application to a display device for color display; the disclosed invention can also be applied to a display device for monochrome display.

Alternatively, as the display element included in the display device, a light-emitting element utilizing electroluminescence can be used. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. The carriers (electrons and holes) are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element. In this embodiment, an organic EL element is used as a light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that an example of an organic EL element as a light-emitting element is described here.

In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes has a light-transmitting property. A transistor and a light-emitting element are formed over a substrate. The light-emitting element can have a top emission structure in which light emission is extracted through the surface opposite to the substrate; a bottom emission structure in which light emission is extracted through the surface on the substrate side; or a dual emission structure in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side, and a light-emitting element having any of these emission structures can be used.

FIGS. 6A and 6B and FIG. 11 illustrate an example of a light-emitting device using a light-emitting element as a display element.

FIG. 6A is a plan view of the light-emitting device, and FIG. 6B is a cross-sectional view taken along dashed-dotted lines S1-T1, S2-T2, and S3-T3 in FIG. 6A. FIG. 11 is a cross-sectional view taken along a dashed-dotted line S4-T4 in FIG. 6A. Note that an electroluminescent layer 542 and a second electrode layer 543 are not illustrated in the plan view in FIG. 6A.

The light-emitting device illustrated in FIGS. 6A and 6B includes, over a substrate 500, a transistor 510, a capacitor 520, and a wiring layer intersection 530. The transistor 510 is electrically connected to a light-emitting element 540. Note that FIGS. 6A and 6B illustrate a bottom-emission light-emitting device in which light from the light-emitting element 540 is extracted through the substrate 500.

Any of the transistors described in Embodiments 1 to 3 can be applied to the transistor 510. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 310 described in Embodiment 1 is used is described. The transistor 510 is a bottom-gate transistor.

The transistor 510 includes gate electrode layers 511 a and 511 b; gate insulating layers 501 and 502; an oxide semiconductor stack 512 including a first oxide semiconductor layer 512 a, an n-type second oxide semiconductor layer 512 b, and a third oxide semiconductor layer 512 c; and conductive layers 513 a and 513 b serving as a source electrode layer and a drain electrode layer. In the second oxide semiconductor layer 512 b, a region in contact with the first oxide semiconductor layer 512 a has a higher n-type impurity concentration than a region in contact with the third oxide semiconductor layer 512 c. In addition, an insulating layer 525 is formed over the transistor 510.

The capacitor 520 includes conductive layers 521 a and 521 b; the gate insulating layers 501 and 502; an oxide semiconductor stack 522 including a first oxide semiconductor layer 522 a, a second oxide semiconductor layer 522 b containing an impurity imparting n-type conductivity, and a third oxide semiconductor layer 522 c; and a conductive layer 523. The gate insulating layers 501 and 502 and the oxide semiconductor stack 522 are sandwiched between the conductive layer 523 and the conductive layers 521 a and 521 b, whereby the capacitor is formed. In the second oxide semiconductor layer 522 b, a region in contact with the first oxide semiconductor layer 522 a has a higher n-type impurity concentration than a region in contact with the third oxide semiconductor layer 522 c.

The wiring layer intersection 530 is an intersection of a conductive layer 533 and the gate electrode layers 511 a and 511 b. The conductive layer 533 and the gate electrode layers 511 a and 511 b intersect with each other with the gate insulating layers 501 and 502 provided therebetween.

In this embodiment, a 30-nm-thick titanium film is used as each of the gate electrode layer 511 a and the conductive layer 521 a, and a 200-nm-thick copper film is used as each of the gate electrode layer 511 b and the conductive layer 521 b. Thus, the gate electrode layer has a stacked-layer structure of the titanium film and the copper film.

In the transistor 510, the second oxide semiconductor layer which functions as a current path (channel) is sandwiched between the first oxide semiconductor layer and the third oxide semiconductor layer which have lower conductivity than the second oxide semiconductor layer. In the second oxide semiconductor layer, a region on the channel side contains the n-type impurity at a higher concentration than a region on the back channel side. Accordingly, the transistor 510 is a buried-channel transistor in which a current path is separated from the interface with the insulating layer, and therefore has high field-effect mobility. In addition, the transistor 510 is a highly reliable transistor in which influence of an interface state which might be formed on the back channel side is reduced and photodegradation (e.g., negative-bias temperature stress photodegradation) is reduced.

An interlayer insulating layer 504 is formed over the transistor 510, the capacitor 520, and the wiring layer intersection 530. Over the interlayer insulating layer 504, a color filter layer 505 is provided in a region overlapping with the light-emitting element 540. An insulating layer 506 functioning as a planarization insulating layer is provided over the interlayer insulating layer 504 and the color filter layer 505.

The light-emitting element 540 having a stacked-layer structure in which a first electrode layer 541, the electroluminescent layer 542, and the second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The first electrode layer 541 and the conductive layer 513 a are in contact with each other in an opening formed in the insulating layer 506 and the interlayer insulating layer 504, which reaches the conductive layer 513 a; thus the light-emitting element 540 and the transistor 510 are electrically connected to each other. Note that a partition 507 is provided so as to cover part of the first electrode layer 541 and the opening.

Further, a 1500-nm-thick photosensitive acrylic film and a 1500-nm-thick photosensitive polyimide film can be used as the insulating layer 506 and the partition 507, respectively.

As the color filter layer 505, for example, a chromatic color light-transmitting resin can be used. As the chromatic color light-transmitting resin, a photosensitive organic resin or a non-photosensitive organic resin can be used. The photosensitive organic resin is preferably used, in which case the number of resist masks can be reduced, which results in the simplification of the process.

Chromatic colors are all colors except achromatic colors such as black, gray, and white. The color filter layer is formed using a material which transmits only light of the chromatic colors. As chromatic color, red, green, blue, or the like can be used. Alternatively, cyan, magenta, yellow, or the like may also be used. “Transmitting only light of a chromatic color” means that light passing through the color filter layer has a peak at a wavelength of the light of the chromatic color. The thickness of the color filter layer may be controlled as appropriate in consideration of the relationship between the concentration of the coloring material to be included and the transmittance of light. For example, the color filter layer 505 may have a thickness greater than or equal to 1500 nm and less than or equal to 2000 nm.

The partition 507 can be formed using an organic insulating material or an inorganic insulating material. It is particularly preferable that the partition 507 be formed using a photosensitive resin material to have an opening over the first electrode layer 541. A sidewall of the opening is preferably formed as a tilted surface with continuous curvature.

The electroluminescent layer 542 may be formed using either a single layer or a stack of a plurality of layers.

A protective film may be formed over the second electrode layer 543 and the partition 507 in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element 540. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

Further, the light-emitting element 540 may be covered with a layer containing an organic compound deposited by an evaporation method so that oxygen, hydrogen, moisture, carbon dioxide, or the like do not enter the light-emitting element 540.

In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

Further, an electronic paper in which electronic ink is driven can be provided as the display device. The electronic paper is also referred to as electrophoretic display device (electrophoretic display) and is advantageous in that it has the same level of readability as plain paper, it has lower power consumption than other display devices, and it can be made thin and lightweight.

An electrophoretic display device can have various modes. An electrophoretic display device includes a plurality of microcapsules dispersed in a solvent, and each microcapsule contains first particles which are positively charged and second particles which are negatively charged. By applying an electric field to the microcapsules, the particles in the microcapsules move in opposite directions to each other and only the color of the particles gathering on one side is displayed. Note that the first particles and the second particles each contain pigment and do not move without an electric field. Moreover, the first particles and the second particles have different colors (which may be colorless).

A dispersion of the above microcapsules in a solvent is referred to as electronic ink. Furthermore, by the use of a color filter or particles that have a pigment, color display is also possible.

The insulating layer 506 functioning as a planarization insulating layer can be formed using an organic material having heat resistance, such as an acrylic resin, polyimide, a benzocyclobutene-based resin, polyamide, or an epoxy resin. Other than such organic materials, it is also possible to use a low-dielectric constant material (low-k material) such as a siloxane-based resin, phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). Note that the insulating layer 506 may be formed by stacking a plurality of insulating layers formed using any of these materials.

There is no particular limitation on the method of forming the insulating layer 506; the following method can be used depending on the material: a sputtering method, spin coating, dipping, spray coating, a droplet discharge method (such as an inkjet method), screen printing, offset printing, or the like.

Materials similar to those of the first electrode layer 4034 and the second electrode layer 4031 illustrated in FIG. 5A or FIG. 5B can be used for the first electrode layer 541 and the second electrode layer 543.

In this embodiment, since the light-emitting device illustrated in FIGS. 6A and 6B has a bottom-emission structure, the first electrode layer 541 has a light-transmitting property and the second electrode layer 543 has a light-reflecting property. Accordingly, in the case of using a metal film as the first electrode layer 541, the film is preferably made thin enough to secure a light-transmitting property; and in the case of using a light-transmitting conductive layer as the second electrode layer 543, a light-reflecting conductive layer is preferably stacked therewith.

A protection circuit for protecting the driver circuit may be provided. The protection circuit is preferably formed using a nonlinear element.

By using any of the transistors described in Embodiments 1 to 3 as described above, the semiconductor device can have a variety of functions.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Embodiment 6

A semiconductor device having an image sensor function of reading data on an object can be manufactured using any of the transistors described in Embodiments 1 to 3.

An example of a semiconductor device having an image sensor function is illustrated in FIG. 7A. FIG. 7A illustrates an equivalent circuit of a photo sensor, and FIG. 7B is a cross-sectional view illustrating part of the photo sensor.

One electrode of a photodiode 602 is electrically connected to a photodiode reset signal line 658, and the other electrode of the photodiode 602 is electrically connected to a gate of a transistor 640. One of a source and a drain of the transistor 640 is electrically connected to a photosensor reference signal line 672, and the other of the source and the drain of the transistor 640 is electrically connected to one of a source and a drain of a transistor 656. A gate of the transistor 656 is electrically connected to a gate signal line 659, and the other of the source and the drain of the transistor 656 is electrically connected to a photosensor output signal line 671.

Note that in circuit diagrams in this specification, a transistor using an oxide semiconductor layer is denoted by a symbol “OS” so that it can be identified as a transistor including an oxide semiconductor layer. In FIG. 7A, the transistor 640 and the transistor 656 are each a transistor using an oxide semiconductor layer, to which any of the transistors described in Embodiments 1 to 3 can be applied. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 310 described in Embodiment 1 is used is described. The transistor 640 is a bottom-gate transistor.

FIG. 7B is a cross-sectional view of the photodiode 602 and the transistor 640 in the photosensor. The photodiode 602 functioning as a sensor and the transistor 640 are provided over a substrate 601 (element substrate) having an insulating surface. A substrate 613 is provided over the photodiode 602 and the transistor 640 with the use of an adhesive layer 608.

An insulating layer 632, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided over the transistor 640. The photodiode 602 includes an electrode layer 641 b formed over the interlayer insulating layer 633, semiconductor films (a first semiconductor film 606 a, a second semiconductor film 606 b, and a third semiconductor film 606 c stacked over the electrode layer 641 b in this order), an electrode layer 642 which is provided over the interlayer insulating layer 634 and electrically connected to the electrode layer 641 b through the first to third semiconductor films, and an electrode layer 641 a which is provided in the same layer as the electrode layer 641 b and electrically connected to the electrode layer 642.

The electrode layer 641 b is electrically connected to a conductive layer 643 formed over the interlayer insulating layer 634, and the electrode layer 642 is electrically connected to a conductive layer 645 through the electrode layer 641 a. The conductive layer 645 is electrically connected to a gate electrode layer of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

Here, a pin photodiode in which a semiconductor film having p-type conductivity as the first semiconductor film 606 a, a high-resistance semiconductor film (i-type semiconductor film) as the second semiconductor film 606 b, and a semiconductor film having n-type conductivity as the third semiconductor film 606 c are stacked is illustrated as an example.

The first semiconductor film 606 a is a p-type semiconductor film and can be formed using an amorphous silicon film containing an impurity element imparting p-type conductivity. The first semiconductor film 606 a is formed by a plasma CVD method with the use of a semiconductor source gas containing an impurity element belonging to Group 13 (e.g., boron (B)). As the semiconductor source gas, silane (SiH₄) may be used. Alternatively, Si₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄, SiF₄, or the like may be used. Further alternatively, an amorphous silicon film which does not contain an impurity element may be formed, and then an impurity element may be introduced into the amorphous silicon film by a diffusion method or an ion implantation method. Heating or the like may be conducted after introducing the impurity element by an ion implantation method or the like in order to diffuse the impurity element. In this case, as a method of forming the amorphous silicon film, an LPCVD method, a vapor deposition method, a sputtering method, or the like may be used. The first semiconductor film 606 a is preferably formed to have a thickness greater than or equal to 10 nm and less than or equal to 50 nm.

The second semiconductor film 606 b is an i-type semiconductor film (intrinsic semiconductor film) and is formed using an amorphous silicon film. As for formation of the second semiconductor film 606 b, an amorphous silicon film is formed by a plasma CVD method with the use of a semiconductor source gas. As the semiconductor source gas, silane (SiH₄) may be used. Alternatively, Si₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄, SiF₄, or the like may be used. The second semiconductor film 606 b may be formed by an LPCVD method, a vapor deposition method, a sputtering method, or the like. The second semiconductor film 606 b is preferably formed to have a thickness greater than or equal to 200 nm and less than or equal to 1000 nm.

The third semiconductor film 606 c is an n-type semiconductor film and is formed using an amorphous silicon film containing an impurity element imparting n-type conductivity. The third semiconductor film 606 c is formed by a plasma CVD method with the use of a semiconductor source gas containing an impurity element belonging to Group 15 (e.g., phosphorus (P)). As the semiconductor source gas, silane (SiH₄) may be used. Alternatively, Si₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄, SiF₄, or the like may be used. Further alternatively, an amorphous silicon film which does not contain an impurity element may be formed, and then an impurity element may be introduced into the amorphous silicon film by a diffusion method or an ion implantation method. Heating or the like may be conducted after introducing the impurity element by an ion implantation method or the like in order to diffuse the impurity element. In this case, as a method of forming the amorphous silicon film, an LPCVD method, a vapor deposition method, a sputtering method, or the like may be used. The third semiconductor film 606 c is preferably formed to have a thickness greater than or equal to 20 nm and less than or equal to 200 nm.

The first semiconductor film 606 a, the second semiconductor film 606 b, and the third semiconductor film 606 c are not necessarily formed using an amorphous semiconductor, and may be formed using a polycrystalline semiconductor or a microcrystalline semiconductor (semi-amorphous semiconductor: SAS).

The mobility of holes generated by the photoelectric effect is lower than the mobility of electrons. Therefore, a pin photodiode has better characteristics when a surface on the p-type semiconductor film side is used as a light-receiving plane. Here, an example in which light received by the photodiode 602 from a surface of the substrate 601, over which the pin photodiode is formed, is converted into electric signals is described. Further, light from the semiconductor film having the conductivity type opposite to that of the semiconductor film on the light-receiving plane is disturbance light; therefore, the electrode layer is preferably formed using a light-blocking conductive layer. A surface on the n-type semiconductor film side can alternatively be used as the light-receiving plane.

In the transistor 640, a second oxide semiconductor layer which functions as a current path (channel) is sandwiched between a first oxide semiconductor layer and a third oxide semiconductor layer which have lower conductivity than the second oxide semiconductor layer. In the second oxide semiconductor layer, a region on the channel side contains the n-type impurity at a higher concentration than a region on the back channel side. Accordingly, the transistor 640 is a buried-channel transistor in which a current path is separated from the interface with the insulating layer, and therefore has high field-effect mobility. In addition, the transistor 640 is a highly reliable transistor in which influence of an interface state which might be formed on the back channel side is reduced and photodegradation (e.g., negative-bias temperature stress photodegradation) is reduced.

With the use of an insulating material, the insulating layer 632, the interlayer insulating layer 633, and the interlayer insulating layer 634 can be formed, depending on the material, using a sputtering method, a plasma CVD method, spin coating, dipping, spray coating, a droplet discharge method (such as an inkjet method), screen printing, offset printing, or the like.

For reduction of surface roughness, an insulating layer functioning as a planarization insulating layer is preferably used as each of the interlayer insulating layers 633 and 634. For the interlayer insulating layers 633 and 634, for example, an organic insulating material having heat resistance, such as polyimide, an acrylic resin, a benzocyclobutene-based resin, polyamide, or an epoxy resin, can be used. Other than such organic insulating materials, it is possible to use a single layer or stacked layers of a low-dielectric constant material (a low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like.

With detection of light that enters the photodiode 602, data on an object can be read. Note that a light source such as a backlight can be used at the time of reading information on an object.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Embodiment 7

A semiconductor device disclosed in this specification can be applied to a variety of electronic appliances (including game machines). Examples of electronic appliances include a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, cameras such as a digital camera and a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio reproducing device, a game machine (e.g., a pachinko machine or a slot machine), a game console, and the like. Specific examples of these electronic appliances are illustrated in FIGS. 8A to 8C.

FIG. 8A illustrates a table 9000 having a display portion. In the table 9000, a display portion 9003 is incorporated in a housing 9001 and an image can be displayed on the display portion 9003. Note that the housing 9001 is supported by four leg portions 9002. Further, a power cord 9005 for supplying power is provided for the housing 9001.

The semiconductor device described in any of the above embodiments can be used in the display portion 9003, so that the electronic appliance can have high reliability.

The display portion 9003 has a touch-input function. When a user touches displayed buttons 9004 which are displayed on the display portion 9003 of the table 9000 with his/her finger or the like, the user can carry out operation of the screen and input of information. Further, when the table may be made to communicate with home appliances or control the home appliances, the table 9000 may function as a control device which controls the home appliances by operation on the screen. For example, with use of the semiconductor device having an image sensor described in Embodiment 3, the display portion 9003 can function as a touch panel.

Further, the screen of the display portion 9003 can be placed perpendicular to a floor with a hinge provided for the housing 9001; thus, the table 9000 can also be used as a television device. When a television device having a large screen is set in a small room, an open space is reduced; however, when a display portion is incorporated in a table, a space in the room can be efficiently used.

FIG. 8B illustrates a television set 9100. In the television set 9100, a display portion 9103 is incorporated in a housing 9101 and an image can be displayed on the display portion 9103. Note that the housing 9101 is supported by a stand 9105 here.

The television set 9100 can be operated with an operation switch of the housing 9101 or a separate remote controller 9110. Channels and volume can be controlled with an operation key 9109 of the remote controller 9110 so that an image displayed on the display portion 9103 can be controlled. Furthermore, the remote controller 9110 may be provided with a display portion 9107 for displaying data output from the remote controller 9110.

The television set 9100 illustrated in FIG. 8B is provided with a receiver, a modem, and the like. With the use of the receiver, the television set 9100 can receive general TV broadcasts. Moreover, when the television set 9100 is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed.

The semiconductor device described in any of the above embodiments can be used in the display portions 9103 and 9107, so that the television set and the remote controller can have high reliability.

FIG. 8C illustrates a computer which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.

The semiconductor device described in any of the above embodiments can be used in the display portion 9203, so that the computer can have high reliability.

FIGS. 9A and 9B illustrate a tablet terminal that can be folded. In FIG. 9A, the tablet terminal is opened, and includes a housing 9630, a display portion 9631 a, a display portion 9631 b, a switch 9034 for switching display modes, a power switch 9035, a switch 9036 for switching to power-saving mode, a clip 9033, and an operation switch 9038.

The semiconductor device described in any of the above embodiments can be used in the display portion 9631 a and the display portion 9631 b, so that the tablet terminal can have high reliability.

Part of the display portion 9631 a can be a touch panel region 9632 a, and data can be input by touching operation keys 9638 that are displayed. Note that FIG. 9A shows, as an example, that half of the area of the display portion 9631 a has only a display function and the other half of the area has a touch panel function. However, the structure of the display portion 9631 a is not limited to this, and all the area of the display portion 9631 a may have a touch panel function. For example, all the area of the display portion 9631 a can display keyboard buttons and serve as a touch panel while the display portion 9631 b can be used as a display screen.

Like the display portion 9631 a, part of the display portion 9631 b can be a touch panel region 9632 b. When a finger, a stylus, or the like touches the place where a button 9639 for switching to keyboard display is displayed in the touch panel, keyboard buttons can be displayed on the display portion 9631 b.

Touch input can be performed concurrently on the touch panel regions 9632 a and 9632 b.

The switch 9034 for switching display modes allows switching between a landscape mode and a portrait mode, color display and black-and-white display, and the like. With the switch 9036 for switching to power-saving mode, the luminance of display can be optimized in accordance with the amount of external light at the time when the tablet terminal is in use, which is detected with an optical sensor incorporated in the tablet terminal. The tablet terminal may include another detection device such as a sensor for detecting orientation (e.g., a gyroscope or an acceleration sensor) in addition to the optical sensor.

Although the display portion 9631 a and the display portion 9631 b have the same display area in FIG. 9A, an embodiment of the present invention is not limited to this example. The display portion 9631 a and the display portion 9631 b may have different areas or different display quality. For example, one of them may be a display panel that can display higher-definition images than the other.

FIG. 9B illustrates the tablet terminal folded, which includes the housing 9630, a solar battery 9633, and a charge and discharge control circuit 9634. Note that FIG. 9B shows an example in which the charge and discharge control circuit 9634 includes the battery 9635 and the DCDC converter 9636.

Since the tablet can be folded in two, the housing 9630 can be closed when the tablet is not in use. Thus, the display portions 9631 a and 9631 b can be protected, thereby providing a tablet with high endurance and high reliability for long-term use.

The tablet terminal illustrated in FIGS. 9A and 9B can have other functions such as a function of displaying various kinds of data (e.g., a still image, a moving image, and a text image), a function of displaying a calendar, a date, the time, or the like on the display portion, a touch-input function of operating or editing the data displayed on the display portion by touch input, and a function of controlling processing by various kinds of software (programs).

The solar battery 9633, which is attached on the surface of the tablet terminal, supplies electric power to a touch panel, a display portion, an image signal processor, and the like. Note that the solar battery 9633 can be provided on one or both surfaces of the housing 9630 and the battery 9635 can be charged efficiently. When a lithium ion battery is used as the battery 9635, there is an advantage of downsizing or the like.

The structure and operation of the charge and discharge control circuit 9634 illustrated in FIG. 9B are described with reference to a block diagram of FIG. 9C. FIG. 9C illustrates the solar battery 9633, the battery 9635, the DCDC converter 9636, a converter 9637, switches SW1 to SW3, and the display portion 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 correspond to the charge and discharge control circuit 9634 in FIG. 9B.

First, an example of operation in the case where power is generated by the solar battery 9633 using external light is described. The voltage of power generated by the solar battery 9633 is raised or lowered by the DCDC converter 9636 so that a voltage for charging the battery 9635 is obtained. When the display portion 9631 is operated with the power from the solar battery 9633, the switch SW1 is turned on and the voltage of the power is raised or lowered by the converter 9637 to a voltage needed for operating the display portion 9631. In addition, when display on the display portion 9631 is not performed, the switch SW1 is turned off and a switch SW2 is turned on so that charge of the battery 9635 may be performed.

Here, the solar battery 9633 is shown as an example of a power generation means; however, there is no particular limitation on a way of charging the battery 9635, and the battery 9635 may be charged with another power generation means such as a piezoelectric element or a thermoelectric conversion element (Peltier element). For example, the battery 9635 may be charged with a non-contact power transmission module that transmits and receives power wirelessly (without contact) to charge the battery or with a combination of other charging means.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

This application is based on Japanese Patent Application serial no. 2012-147178 filed with Japan Patent Office on Jun. 29, 2012, the entire contents of which are hereby incorporated by reference. 

1. (canceled)
 2. A pellet-like particle comprising: a first layer including gallium, zinc and oxygen; a second layer including indium and oxygen; and a third layer including gallium, zinc and oxygen, wherein the second layer is between the first layer and the third layer, wherein each one of the first layer and the third layer is an outermost surface of the pellet-like particle, and wherein the pellet-like particle has a crystal structure.
 3. The pellet-like particle according to claim 2, wherein the second layer includes a series of 2 to 100 indium atoms in a lateral direction.
 4. The pellet-like particle according to claim 2, wherein the second layer includes a series of 2 to 500 indium atoms in a lateral direction.
 5. The pellet-like particle according to claim 2, the pellet-like particle has a hexagonal shape.
 6. A flat-plate-like particle comprising: a first layer including gallium, zinc and oxygen; a second layer including indium and oxygen; and a third layer including gallium, zinc and oxygen, wherein the second layer is between the first layer and the third layer, wherein each one of the first layer and the third layer is an outermost surface of the flat-plate-like particle, and wherein the flat-plate-like particle has a crystal structure.
 7. The flat-plate-like particle according to claim 6, wherein the second layer includes a series of 2 to 100 indium atoms in a lateral direction.
 8. The flat-plate-like particle according to claim 6 wherein the second layer includes a series of 2 to 500 indium atoms in a lateral direction.
 9. The flat-plate-like particle according to claim 6, the flat-plate-like particle has a hexagonal shape.
 10. A non-single crystal semiconductor layer comprising: a plurality of pellet-like particles formed over a surface, the plurality of pellet-like particles comprising: a plurality of first pellet-like particles; and a plurality of second pellet-like particles stacked over the plurality of first pellet-like particles, wherein the plurality of first pellet-like particles and the plurality of second pellet-like particles are arranged to be substantially parallel to the surface, wherein each one of the plurality of pellet-like particles comprises: a first layer including gallium, zinc and oxygen; a second layer including indium and oxygen; and a third layer including gallium, zinc and oxygen, wherein the second layer is between the first layer and the third layer, wherein each one of the first layer and the third layer is an outermost surface of each one of the plurality of pellet-like particles, and wherein the plurality of pellet-like particles has a crystal structure.
 11. A semiconductor device comprising the non-single crystal semiconductor layer according to claim 10, the semiconductor device further comprising: a gate electrode layer; a gate insulating layer between the gate electrode layer and the non-single crystal semiconductor layer; and a source electrode layer and a drain electrode layer electrically connected to the non-single crystal semiconductor layer.
 12. The semiconductor device according to claim 11, further comprising: a second oxide semiconductor layer; and a third oxide semiconductor layer, wherein the non-single crystal semiconductor layer is between the second oxide semiconductor layer and the third oxide semiconductor layer.
 13. The semiconductor device according to claim 12, wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer comprises indium.
 14. The non-single crystal semiconductor layer according to claim 10, wherein the second layer includes a series of 2 to 100 indium atoms in a lateral direction.
 15. The non-single crystal semiconductor layer according to claim 10, wherein the second layer includes a series of 2 to 500 indium atoms in a lateral direction.
 16. The non-single crystal semiconductor layer according to claim 10, wherein the non-single crystal semiconductor layer has a c-axis orientation.
 17. The non-single crystal semiconductor layer according to claim 10, wherein each one of the plurality of pellet-like particles has a hexagonal shape.
 18. A non-single crystal semiconductor layer comprising: a plurality of flat-plate-like particles formed over a surface, the plurality of flat-plate-like particles comprising: a first flat-plate-like particles; and a second flat-plate-like particles stacked over the first flat-plate-like particles, wherein the first flat-plate-like particles and the second flat-plate-like particles are arranged to be substantially parallel to the surface, wherein each one of the plurality of flat-plate-like particles comprises: a first layer including gallium, zinc and oxygen; a second layer over and in direct contact with the first layer, the second layer including indium and oxygen; and a third layer over and in direct contact with the second layer, the third layer including gallium, zinc and oxygen, wherein each one of the first layer and the third layer is an outermost surface of the each one of the plurality of flat-plate-like particles, and wherein the plurality of flat-plate-like particles has a crystal structure.
 19. A semiconductor device comprising the non-single crystal semiconductor layer according to claim 18, the semiconductor device further comprising: a gate electrode layer; a gate insulating layer between the gate electrode layer and the non-single crystal semiconductor layer; and a source electrode layer and a drain electrode layer electrically connected to the non-single crystal semiconductor layer.
 20. The semiconductor device according to claim 19, further comprising: a second oxide semiconductor layer; and a third oxide semiconductor layer, wherein the non-single crystal semiconductor layer is between the second oxide semiconductor layer and the third oxide semiconductor layer.
 21. The semiconductor device according to claim 20, wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer comprises indium.
 22. The non-single crystal semiconductor layer according to claim 18, wherein the second layer includes a series of 2 to 100 indium atoms in a lateral direction.
 23. The non-single crystal semiconductor layer according to claim 18, wherein the second layer includes a series of 2 to 500 indium atoms in a lateral direction.
 24. The non-single crystal semiconductor layer according to claim 18, wherein the non-single crystal semiconductor layer has a c-axis orientation.
 25. The non-single crystal semiconductor layer according to claim 18, wherein each one of the plurality of flat-plate-like particles has a hexagonal shape. 